MT91L62AS datasheet, PDF - EEWORLD Datasheet

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MT91L62AS: Description3 Volt Single Rail Codec; CategoryWireless rf/communication Telecom circuit; File Size392KB，19 Pages; ManufacturerZarlink Semiconductor (Microsemi); Websitehttp://www.zarlink.com/

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MT91L62AS Overview

3 Volt Single Rail Codec

MT91L62AS Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Zarlink Semiconductor (Microsemi)
package instruction	SOP, SOP20,.4
Reach Compliance Code	compli
Is Samacsys	N
Law of compression and extension	A/MU-LAW
filter	YES
Maximum gain tolerance	1.6 dB
JESD-30 code	R-PDSO-G20
JESD-609 code	e0
length	12.8 mm
linear encoding	NOT AVAILABLE
Humidity sensitivity level	1
Number of functions	1
Number of terminals	20
Operating mode	SYNCHRONOUS/ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP20,.4
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	240
power supply	3 V
Certification status	Not Qualified
Maximum seat height	2.65 mm
Maximum slew rate	0.01 mA
Nominal supply voltage	3 V
surface mount	YES
technology	CMOS
Telecom integrated circuit types	PROGRAMMABLE CODEC
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	7.5 mm
Base Number Matches	1

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MT91L62

ISO

- CMOS

3 Volt Single Rail Codec

Data Sheet

Features

•

Single 2.7-3.6 volt supply

Programmable

µ−law/A-law

Codec and filters

Fully differential to output driver

SSI digital interface

Individual transmit and receive mute controls

0 dB gain in receive path

6 dB gain in transmit path

Low power operation

ITU-T G.714 compliant

Ordering Information

MT91L62AE

MT91L62AS

MT91L62AN

20 Pin Plastic DIP (300 mil)

20 Pin SOIC

20 Pin SSOP

July 2004

-40°C to +85°C

Description

The MT91L62 3 V single rail Codec incorporates a

built-in Filter/Codec, transmit anti-alias filter, a

reference voltage and bias source. The device

supports both A-law and

µ-law

requirements. The

MT91L62 is a true 3 V device employing a fully

differential architecture to ensure wide dynamic range.

An analog output driver is provided, capable of driving

a 20 k ohm load.

The MT91L62 is fabricated in Zarlink's ISO

-CMOS

technology ensuring low power consumption and high

reliability.

Applications

•

Cellular radio sets

Local area communications stations

Line cards

Battery operated equipment

FILTER/CODEC GAIN

VDD

VSSA

VBias

VRef

AIN+

ENCODER

DECODER

6dB

0 dB

Analog

Interface

AIN-

AOUT +

AOUT -

Din

Dout

STB

CLOCKin

PCM

Serial

Interface

Timing

Control

PWRST

A/µ

CSL0

CSL1 CSL2 RXMute TXMute

Figure 1 - Functional Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

MT91L62

Analog Interfaces

Standard interfaces are provided by the MT91L62. These are:

•

Data Sheet

The analog inputs (transmitter), pins AIN+/AIN-. The maximum peak to peak input is 2.123 Vpp

µ−law

across AIN+/AIN- and 2.2 Vpp A-law across these pins.

The analog outputs (receiver), pins AOUT+/AOUT-. This internally compensated fully differential output

driver is capable of driving a load of 20 k ohms.

PCM Serial Interface

A serial link is required to transport data between the MT91L62 and an external digital transmission device. The

MT91L62 utilizes the strobed data interface found on many standard Codec devices. This interface is commonly

referred to as Simple Serial Interface (SSI).

The bit clock rate is selected by setting the CSL2-0 control pins as shown in Figure 2.

Quiet Code

The PCM serial port can be made to send quiet code to the decoder and receive filter path by setting the RxMute

pin high. Likewise, the PCM serial port will send quiet code in the transmit path when the TxMute pin is high. When

either of these pins are low their respective paths function normally. The -Zero entry of Table 1 is used for the quiet

code definition.

External Clock

Bit Rate (kHz)

128

256

512

1536

2048

4096

CLOCKin

(kHz)

4096

512

1536

2048

4096

CSL

Table 2 - Bit Clock Rate Selection

SSI Mode

The SSI BUS consists of input and output serial data streams named Din and Dout respectively, a Clock input

signal (CLOCKin), and a framing strobe input (STB). A 4.096 MHz master clock is also required for SSI operation if

the bit clock is less than 512 kHz. The timing requirements for SSI are shown in Figures 5 & 6.

In SSI mode the MT91L62 supports only B-Channel operation. Hence, in SSI mode transmit and receive B-Channel

data are always in the channel defined by the STB input.

The data strobe input STB determines the 8-bit timeslot used by the device for both transmit and receive data. This

is an active high signal with an 8 kHz repetition rate.

SSI operation is separated into two categories based upon the data rate of the available bit clock. If the bit clock is

512 kHz or greater then it is used directly by the internal MT91L62 functions allowing synchronous operation. If the

available bit clock is 128 kHz or 256 kHz, then a 4096 kHz master clock is required to derive clocks for the internal

MT91L62 functions.

Zarlink Semiconductor Inc.

MT91L62AS Related Products

	MT91L62AS	MT91L62AN	MT91L62AE	MT91L62
Description	3 Volt Single Rail Codec	3 Volt Single Rail Codec	3 Volt Single Rail Codec	3 Volt Single Rail Codec
Is it Rohs certified?	incompatible	incompatible	incompatible	-
Maker	Zarlink Semiconductor (Microsemi)	Zarlink Semiconductor (Microsemi)	Zarlink Semiconductor (Microsemi)	-
package instruction	SOP, SOP20,.4	SSOP, SSOP20,.3	DIP, DIP20,.3	-
Reach Compliance Code	compli	compli	compli	-
Is Samacsys	N	N	N	-
Law of compression and extension	A/MU-LAW	A/MU-LAW	A/MU-LAW	-
filter	YES	YES	YES	-
Maximum gain tolerance	1.6 dB	1.6 dB	1.6 dB	-
JESD-30 code	R-PDSO-G20	R-PDSO-G20	R-PDIP-T20	-
JESD-609 code	e0	e0	e0	-
length	12.8 mm	7.2 mm	25.195 mm	-
linear encoding	NOT AVAILABLE	NOT AVAILABLE	NOT AVAILABLE	-
Number of functions	1	1	1	-
Number of terminals	20	20	20	-
Operating mode	SYNCHRONOUS/ASYNCHRONOUS	SYNCHRONOUS/ASYNCHRONOUS	SYNCHRONOUS/ASYNCHRONOUS	-
Maximum operating temperature	85 °C	85 °C	85 °C	-
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-
encapsulated code	SOP	SSOP	DIP	-
Encapsulate equivalent code	SOP20,.4	SSOP20,.3	DIP20,.3	-
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	-
Package form	SMALL OUTLINE	SMALL OUTLINE, SHRINK PITCH	IN-LINE	-
Peak Reflow Temperature (Celsius)	240	240	225	-
power supply	3 V	3 V	3 V	-
Certification status	Not Qualified	Not Qualified	Not Qualified	-
Maximum seat height	2.65 mm	2 mm	5.33 mm	-
Maximum slew rate	0.01 mA	0.01 mA	0.01 mA	-
Nominal supply voltage	3 V	3 V	3 V	-
surface mount	YES	YES	NO	-
technology	CMOS	CMOS	CMOS	-
Telecom integrated circuit types	PROGRAMMABLE CODEC	PROGRAMMABLE CODEC	PROGRAMMABLE CODEC	-
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	-
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	-
Terminal form	GULL WING	GULL WING	THROUGH-HOLE	-
Terminal pitch	1.27 mm	0.65 mm	2.54 mm	-
Terminal location	DUAL	DUAL	DUAL	-
Maximum time at peak reflow temperature	30	30	30	-
width	7.5 mm	5.3 mm	7.62 mm	-
Base Number Matches	1	1	1	-

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