MT91L62
ISO
2
- CMOS
3 Volt Single Rail Codec
Data Sheet
Features
•
•
•
•
•
•
•
•
•
Single 2.7-3.6 volt supply
Programmable
µ−law/A-law
Codec and filters
Fully differential to output driver
SSI digital interface
Individual transmit and receive mute controls
0 dB gain in receive path
6 dB gain in transmit path
Low power operation
ITU-T G.714 compliant
Ordering Information
MT91L62AE
MT91L62AS
MT91L62AN
20 Pin Plastic DIP (300 mil)
20 Pin SOIC
20 Pin SSOP
July 2004
-40°C to +85°C
Description
The MT91L62 3 V single rail Codec incorporates a
built-in Filter/Codec, transmit anti-alias filter, a
reference voltage and bias source. The device
supports both A-law and
µ-law
requirements. The
MT91L62 is a true 3 V device employing a fully
differential architecture to ensure wide dynamic range.
An analog output driver is provided, capable of driving
a 20 k ohm load.
The MT91L62 is fabricated in Zarlink's ISO
2
-CMOS
technology ensuring low power consumption and high
reliability.
Applications
•
•
•
•
Cellular radio sets
Local area communications stations
Line cards
Battery operated equipment
FILTER/CODEC GAIN
VDD
VSSA
VBias
VRef
AIN+
ENCODER
DECODER
6dB
0 dB
Analog
Interface
AIN-
AOUT +
AOUT -
Din
Dout
STB
CLOCKin
PCM
Serial
Interface
Timing
Control
PWRST
IC
A/µ
CSL0
CSL1 CSL2 RXMute TXMute
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1999-2004, Zarlink Semiconductor Inc. All Rights Reserved.
MT91L62
Data Sheet
VBias
VRef
PWRST
IC
A/µ
RXMute
TXMute
CSL0
CSL1
CSL2
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
AIN+
AIN-
VSS
AOUT +
AOUT -
VDD
CLOCKin
STB
Din
Dout
20 PIN PDIP/SOIC/SSOP
Figure 2 - Pin Connections
Pin Description
Pin #
1
2
3
4
5
6
7
8
9
10
11
Name
V
Bias
V
Ref
Description
Bias Voltage (Output).
(V
DD
/2) volts is available at this pin for biasing external amplifiers.
Connect 0.1
µ
F capacitor to V
SS
.
Reference Voltage for Codec (Output).
Nominally [(V
DD
/2)-1.1] volts. Used internally.
Connect 0.1
µ
F capacitor to V
SS
.
Internal Connection.
Tie externally to V
SS
for normal operation.
A/µ Law Selection.
CMOS level compatable input pin governs the companding law used by the
device. A-law selected when pin tied to V
DD
or
µ-law
selected when pin tied to V
SS
.
PWRST
Power-up Reset.
Resets internal state of device via Schmitt Trigger input (active low).
IC
A/µ
RXMute
Receive Mute.
When 1, the transmit PCM is forced to negative zero code. When 0, normal
operation. CMOS level compatable input.
TXMute
Transmit Mute.
When 1, the transmit PCM is forced to negative zero code. When 0, normal
operation. CMOS level compatable input.
CSL0
CSL1
CSL2
D
out
Clock Speed Select.
These pins are used to program the speed of the SSI mode as well as the
conversion rate between the externally supplied MCL clock and the 512 KHz clock required by a
filter/codec. Refer to Table 2 for details. CMOS level compatable input.
Data Output.
A tri-state digital output for 8-bit wide channel data being sent to the Layer 1
device. Data is shifted out via the pin concurrent with the rising edge of BCL during the timeslot
defined by STB.
Data Input.
A digital input for 8-bit wide data from the layer 1 device. Data is sampled on the
falling edge of BCL during the timeslot defined by STB. CMOS level compatable input.
Data Strobe.
This input determines the 8-bit timeslot used by the device for both transmit and
receive data. This active high signal has a repetition rate of 8 kHz. CMOS level compatable
input.
12
13
D
in
STB
14
CLOCKin
Clock (Input).
The clock provided to this input pin is used by the internal device functions.
Connect bit clock to this pin when it is 512 kHz or greater. Connect a 4096 kHz clock to this pin
when the bit clock is 128 kHz or 256 kHz. CMOS level compatable input.
V
DD
AOUT-
AOUT+
V
SS
Positive Power Supply.
Nominally 3 volts.
Inverting Analog Output.
(balanced).
Non-Inverting Analog Output.
(balanced).
Ground.
Nominally 0 volts.
15
16
17
18
2
Zarlink Semiconductor Inc.
MT91L62
Pin Description (continued)
Pin #
19
20
Name
Ain-
Ain+
Description
Inverting Analog Input.
No external anti-aliasing is required.
Data Sheet
Non-Inverting Analog Input.
Non-inverting input. No external anti-aliasing is required.
Overview
The 3 V Single-Rail Codec features complete Analog/Digital and Digital/Analog conversion of audio signals
(Filter/Codec) and an analog interface to a standard analog transmitter and receiver (analog Interface). The
receiver amplifier is capable of driving a 20 k ohm load.
Functional Description
Filter/Codec
The Filter/Codec block implements conversion of the analog 0-3.3 kHz speech signals to/from the digital domain
compatible with 64 kb/s PCM B-Channels. Selection of companding curves and digital code assignment are
programmable. These are ITU-T G.711 A-law or
µ-Law,
with true-sign/Alternate Digit Inversion.
The Filter/Codec block also implements a transmit audio path gain in the analog domain. Figure 3 depicts the
nominal half-channel for the MT91L62.
The internal architecture is fully differential to provide the best possible noise rejection as well as to allow a wide
dynamic range from a single 3 volt supply design. This fully differential architecture is continued into the Analog
Interface section to provide full chip realization of these capabilities for the external functions.
A reference voltage (V
Ref
), for the conversion requirements of the Codec section, and a bias voltage (V
Bias
), for
biasing the internal analog sections, are both generated on-chip. V
Bias
is also brought to an external pin so that it
may be used for biasing external gain setting amplifiers. A 0.1
µF
capacitor must be connected from V
Bias
to analog
ground at all times. Likewise, although V
Ref
may only be used internally, a 0.1
µF
capacitor from the V
Ref
pin to
ground is required at all times. The analog ground reference point for these two capacitors must be physically the
same point. To facilitate this the V
Ref
and V
Bias
pins are situated on adjacent pins.
The transmit filter is designed to meet ITU-T G.714 specifications. An anti-aliasing filter is included. This is a
second order lowpass implementation with a corner frequency at 25 kHz.
The receive filter is designed to meet ITU-T G.714 specifications. Filter response is peaked to compensate for the
sinx/x attenuation caused by the 8 kHz sampling rate.
Companding law selection for the Filter/Codec is provided by the A/µ companding control pin. Table 1
illustrates these choices.
ITU-T (G.711)
µ-Law
1000 0000
1111 1111
0111 1111
0000 0000
Code
+ Full Scale
+ Zero
-Zero
(quiet code)
- Full Scale
A-Law
1010 1010
1101 0101
0101 0101
0010 1010
Table 1 - Law Selection
3
Zarlink Semiconductor Inc.
MT91L62
Analog Interfaces
Standard interfaces are provided by the MT91L62. These are:
•
•
Data Sheet
The analog inputs (transmitter), pins AIN+/AIN-. The maximum peak to peak input is 2.123 Vpp
µ−law
across AIN+/AIN- and 2.2 Vpp A-law across these pins.
The analog outputs (receiver), pins AOUT+/AOUT-. This internally compensated fully differential output
driver is capable of driving a load of 20 k ohms.
PCM Serial Interface
A serial link is required to transport data between the MT91L62 and an external digital transmission device. The
MT91L62 utilizes the strobed data interface found on many standard Codec devices. This interface is commonly
referred to as Simple Serial Interface (SSI).
The bit clock rate is selected by setting the CSL2-0 control pins as shown in Figure 2.
Quiet Code
The PCM serial port can be made to send quiet code to the decoder and receive filter path by setting the RxMute
pin high. Likewise, the PCM serial port will send quiet code in the transmit path when the TxMute pin is high. When
either of these pins are low their respective paths function normally. The -Zero entry of Table 1 is used for the quiet
code definition.
External Clock
Bit Rate (kHz)
128
256
512
1536
2048
4096
CLOCKin
(kHz)
4096
4096
512
1536
2048
4096
CSL
2
1
1
0
0
0
0
CSL
1
0
0
0
0
1
1
CSL
0
0
1
0
1
0
1
Table 2 - Bit Clock Rate Selection
SSI Mode
The SSI BUS consists of input and output serial data streams named Din and Dout respectively, a Clock input
signal (CLOCKin), and a framing strobe input (STB). A 4.096 MHz master clock is also required for SSI operation if
the bit clock is less than 512 kHz. The timing requirements for SSI are shown in Figures 5 & 6.
In SSI mode the MT91L62 supports only B-Channel operation. Hence, in SSI mode transmit and receive B-Channel
data are always in the channel defined by the STB input.
The data strobe input STB determines the 8-bit timeslot used by the device for both transmit and receive data. This
is an active high signal with an 8 kHz repetition rate.
SSI operation is separated into two categories based upon the data rate of the available bit clock. If the bit clock is
512 kHz or greater then it is used directly by the internal MT91L62 functions allowing synchronous operation. If the
available bit clock is 128 kHz or 256 kHz, then a 4096 kHz master clock is required to derive clocks for the internal
MT91L62 functions.
4
Zarlink Semiconductor Inc.
MT91L62
Data Sheet
Applications where Bit Clock (BCL) is below 512 kHz are designated as asynchronous. The MT91L62 will re-align
its internal clocks to allow operation when the external master and bit clocks are asynchronous. Control pins CSL2,
CSL1 and CSL0 are used to program the bit rates.
For synchronous operation, data is sampled from Din, on the falling edge of BCL during the time slot defined by the
STB input. Data is made available, on Dout, on the rising edge of BCL during the time slot defined by the STB input.
Dout is tri-stated at all times when STB is not true. If STB is valid, then quiet code will be transmitted on Dout during
the valid strobe period. There is no frame delay through the PCM serial circuit for synchronous operation.
For asynchronous operation Dout and Din are as defined for synchronous operation except that the allowed
output jitter on Dout is larger. This is due to the resynchronization circuitry activity and will not affect operation
since the bit cell period at 128 kb/s and 256 kb/s is relatively large. There is a one frame delay through the PCM
serial circuit for asynchronous operation. Refer to the specifications of Figures 5 & 6 for both synchronous and
asynchronous SSI timing.
PWRST
While the MT91L62 is held in PWRST no device control or functionality is possible.
Serial
Port
Filter/Codec and Analog Interface
Default Bypass
Aout +
Decoder
Receive
Filter Gain
0 dB
0 dB
Receiver
Driver
20kΩ
PCM
D
in
Aout-
PCM
D
out
Transmit Gain
Encoder
6 dB
AIN+
AIN-
Analog
Input
Internal To Device
External To Device
Figure 3 - Audio Gain Partitioning
5
Zarlink Semiconductor Inc.
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