MT91L61ASR1 datasheet, PDF - EEWORLD Datasheet

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MT91L61ASR1: Description3 Volt Multi-Featured Codec (MFC); CategoryWireless rf/communication Telecom circuit; File Size517KB，33 Pages; ManufacturerZarlink Semiconductor (Microsemi); Websitehttp://www.zarlink.com/; Environmental Compliance

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MT91L61ASR1 Overview

3 Volt Multi-Featured Codec (MFC)

MT91L61ASR1 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Zarlink Semiconductor (Microsemi)
package instruction	SOP, SOP24,.4
Reach Compliance Code	unknown
Law of compression and extension	A/MU-LAW
filter	YES
Maximum gain tolerance	0.2 dB
JESD-30 code	R-PDSO-G24
JESD-609 code	e3
length	15.4 mm
linear encoding	NOT AVAILABLE
Number of functions	1
Number of terminals	24
Operating mode	SYNCHRONOUS/ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP24,.4
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
power supply	3 V
Certification status	Not Qualified
Maximum seat height	2.65 mm
Maximum slew rate	0.01 mA
Nominal supply voltage	3 V
surface mount	YES
technology	CMOS
Telecom integrated circuit types	PROGRAMMABLE CODEC
Temperature level	INDUSTRIAL
Terminal surface	MATTE TIN
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
width	7.5 mm
Base Number Matches	1

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ISO

-CMOS

MT91L60/61

3 Volt Multi-Featured Codec (MFC)

Data Sheet

Features

•

Single 2.7-3.6 volt supply operation

MT91L61 version features a delayed framing

pulse in SSI and ST-BUS modes to facilitate

cascaded devices

Programmable

µ-Law/A-Law

Codec and Filters

Programmable ITU-T (G.711)/sign-magnitude

coding

Programmable transmit, receive and side-tone

gains

Fully differential interface to handset transducers

- including 300 ohm receiver driver

Flexible digital interface including ST-BUS/SSI

Serial microport

Low power operation

ITU-T G.714 compliant

Multiple power down modes

Ordering Information

MT91L61AE

24 Pin PDIP

MT91L60AE

24 Pin PDIP

MT91L61AS

24 Pin SOIC

MT91L60AS

20 Pin SOIC

MT91L61AN

24 Pin SSOP

MT91L60AN

20 Pin SSOP

MT91L60ASR

20 Pin SOIC

MT91L61ASR

24 Pin SOIC

MT91L61ASR1 24 Pin SOIC*

MT9160AN1

20 Pin SSOP*

*Pb Free Matte Tin

-40°C to +85°C

March 2006

•

Tubes

Tape & Reel

Tubes

Applications

•

Battery operated equipment

Digital telephone sets

Cellular radio sets

Local area communications stations

Pair Gain Systems

Line cards

VSSD

VDD

VSSA

VBias

VRef

FILTER/CODEC GAIN

M-

ENCODER

DECODER

7dB

-7dB

Transducer

Interface

M+

HSPKR +

HSPKR -

Din

Dout

STB/F0i

CLOCKin

STBd/FOod

(MT91L61only)

Flexible

Digital

Interface

Timing

ST-BUS

C&D

Channels

Serial Microport

A/µ/IRQ

PWRST

DATA1

DATA2

SCLK

Figure 1 - Functional Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

MT91L60/61

Functional Description

Filter/Codec

Data Sheet

The Filter/Codec block implements conversion of the analog 0-3.3 kHz speech signals to/from the digital domain

compatible with 64 kb/s PCM B-Channels. Selection of companding curves and digital code assignment are

programmable. These are ITU-T G.711 A-law or

µ-Law,

with true-sign/Alternate Digit Inversion or true-sign/Inverted

Magnitude coding, respectively. Optionally, sign-magnitude coding may also be selected for proprietary

applications.

The Filter/Codec block also implements transmit and receive audio path gains in the analog domain. A

programmable gain, voice side-tone path is also included to provide proportional transmit speech feedback to the

handset receiver. This side tone path feature is disabled by default. Figure 3 depicts the nominal half-channel and

side-tone gains for the MT91L60/61.

In the event of PWRST, the MT91L60/61 defaults such that the side-tone path is off, all programmable gains are set

to 0dB and ITU-T

µ-Law

is selected. Further, the digital port is set to SSI mode operation at 2048 kb/s and the FDI

and driver sections are powered up. (See Microport section.)

The internal architecture is fully differential to provide the best possible noise rejection as well as to allow a wide

dynamic range from a single 3 volt supply design. This fully differential architecture is continued into the Transducer

Interface section to provide full chip realization of these capabilities for the handset functions.

A reference voltage (V

Ref

), for the conversion requirements of the Codec section, and a bias voltage (V

Bias

), for

biasing the internal analog sections, are both generated on-chip. V

Bias

is also brought to an external pin so that it

may be used for biasing external gain setting amplifiers. A 0.1µF capacitor must be connected from V

Bias

to analog

ground at all times. Although V

Ref

may only be used internally, a 0.1µF capacitor must be connected from V

Ref

ground. The analog ground reference point for these two capacitors must be physically the same point. To facilitate

this the V

Ref

and V

Bias

pins are situated on adjacent pins.

The transmit filter is designed to meet ITU-T G.714 specifications. The nominal gain for this filter is 0 dB (gain

control = 0 dB). Gain control allows the output signal to be increased up to 7 dB. An anti-aliasing filter is included.

This is a second order lowpass implementation with a corner frequency at 25 kHz.

The receive filter is designed to meet ITU-T G.714 specifications. The nominal gain for this filter is 0 dB (gain control

= 0 dB). Gain control allows the output signal to be attenuated up to 7 dB. Filter response is peaked to compensate

for the sinx/x attenuation caused by the 8 kHz sampling rate.

Side-tone is derived from the input of the Tx filter and is not subject to the gain control of the Tx filter section. Side-

tone is summed into the receive handset transducer driver path after the Rx filter gain control section so that Rx

gain adjustment will not affect side-tone levels. The side-tone path may be enabled/disabled with the gain control

bits located in Gain Control Register 2 (address 01h).

Transmit and receive filter gains are controlled by the TxFG

-TxFG

and RxFG

-RxFG

control bits, respectively.

These are located in Gain Control Register 1 (address 00h). Transmit filter gain is adjustable from 0dB to +7dB and

receive filter gain from 0dB to -7dB, both in 1dB increments.

Side-tone filter gain is controlled by the STG

-STG

control bits located in Gain Control Register 2 (address 01h).

Side-tone gain is adjustable from

-9.96 dB to +9.96 dB in 3.32 dB increments.

Companding law selection for the Filter/Codec is provided by the A/µ companding control bit while the coding

scheme is controlled by the Smag/ITU-T control bit. The A/µ control bit is logically OR’ed with the A/µ pin providing

access in both controller and controllerless modes. Both A/µ and Smag/ITU-T reside in Control Register 2 (address

04h). Table 1 illustrates these choices.

Zarlink Semiconductor Inc.

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