MX29GA321E C/F
MX29GA321E C/F
DATASHEET
P/N:PM1511
REV. 0.01, AUG. 28, 2009
1
ADVANCED INFORMATION
MX29GA321E C/F
SINGLE VOLTAGE 3V ONLY FLASH MEMORY
FEATURES
GENERAL FEATURES
• Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
- V I/O voltage must tight with VCC
- V I/O=VCC=2.7V~3.6V
• Byte/Word mode switchable
- 2,097,152 x 16
• 64 x 32K word uniform sector
• 8-word page read buffer
• 16-word write buffer
• Latch-up protected to 100mA from -1V to 1.5xVcc
• Low Vcc write inhibit : Vcc ≤ VLKO
• Compatible with JEDEC standard
- Pinout and software compatible to single power supply Flash
• Deep power down mode
PERFORMANCE
• High Performance
- Fast access time: 70ns
- Page access time: 25ns
- Fast program time: 11us/word
- Fast erase time: 0.6s/sector
• Low Power Consumption
- Low active read current: 30mA (typical) at 5MHz
- Low standby current: 30uA (typical)
• Typical 100,000 erase/program cycle
• 20 years data retention
SOFTWARE FEATURES
• Program/Erase Suspend & Program/Erase Resume
- Suspends sector erase operation to read data from or program data to another sector which is not being
erased
- Suspends sector program operation to read data from another sector which is not being program
• Status Reply
- Data# Polling & Toggle bits provide detection of program and erase operation completion
• Support Common Flash Interface (CFI)
HARDWARE FEATURES
• Ready/Busy# (RY/BY#) Output
- Provides a hardware method of detecting program and erase operation completion
• Hardware Reset (RESET#) Input
- Provides a hardware method to reset the internal state machine to read mode
• WP#/ACC input pin
- Hardware write protect pin/Provides accelerated program capability
SECURITY
• Extra 128-word sector for security
- Features factory locked and identifiable, and customer lockable
• Advanced sector protection/unprotection function (Solid and Password Protect)
- Provides sector protect/unprotect function to disable or enable program or erase operation in the sector
• Advanced read protection function (Password protection & Crypto engine)
- Provides read lock feature to protect sectors against the unauthorized reading of memory
Please contact Macronix sales for specific information regarding this advanced sector write and read
protection feature.
P/N:PM1511
REV. 0.01, AUG. 28, 2009
2
MX29GA321E C/F
PACKAGE
• 64-Ball FBGA (10mm x 13mm)
•
All Pb-free devices are RoHS Compliant
PIN CONFIGURATION
64 FBGA
A
1
2
3
4
5
6
7
8
A0
A5
A7
WP#/
ACC
CE#
A12
VCC
A17
NC
B
C
A1
GND
A8
A13
NC
A18
NC
A2
A6
A9
A11
A14
NC
A19
A20
D
A3
A4
A10
RES-
ET#
Q3
NC
NC
A15
A16
E
Q8
Q1
Q9
Q4
NC
Q15
RY/
BY#
OE#
F
NC
Q0
Q10
Q11
Q12
NC
NC
G
NC
NC
Q2
V I/O
Q5
Q6
Q14
WE#
H
NC
NC
VCC
GND
Q13
GND
Q7
NC
PIN DESCRIPTION
PIN NAME
Address Input
Data Inputs/Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
Hardware Reset Pin, Active Low
Hardware Write Protect/Programming
WP#/ACC*
Acceleration input
RY/BY# Read/Busy Output
VCC
+3.0V single power supply
GND
Device Ground
NC
Pin Not Connected Internally
VI/O*
Power Supply for Input/Output
Notes:
1. WP#/ACC has internal pull up.
2. VI/O=VCC=2.7V~3.6V
P/N:PM1511
LOGIC SYMBOL
21
A0-A20
Q0-Q15
(A-1)
16 or 8
SYMBOL
A0~A20
Q0~Q15
CE#
WE#
OE#
RESET#
CE#
OE#
WE#
RESET#
WP#/ACC
BYTE#
VI/O
RY/BY#
REV. 0.01, AUG. 28, 2009
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MX29GA321E C/F
BLOCK DIAGRAM
CE#
OE#
WE#
RESET#
BYTE#
WP#/ACC
CONTROL
INPUT
LOGIC
WRITE
PROGRAM/ERASE
HIGH VOLTAGE
STATE
MACHINE
(WSM)
STATE
FLASH
ARRAY
ARRAY
Y-PASS GATE
SOURCE
HV
COMMAND
DATA
DECODER
REGISTER
X-DECODER
ADDRESS
LATCH
A0-AM
AND
BUFFER
SENSE
AMPLIFIER
Y-DECODER
PGM
DATA
HV
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
Q0-Q15/A-1
I/O BUFFER
AM: MSB address
P/N:PM1511
REV. 0.01, AUG. 28, 2009
4
MX29GA321E C/F
BLOCK DIAGRAM DESCRIPTION
The block diagram on Page 4 illustrates a simplified architecture of this device. Each block in the block diagram
represents one or more circuit modules in the real chip used to access, erase, program, and read the memory
array.
The "CONTROL INPUT LOGIC" block receives input pins CE#, OE#, WE#, RESET#, and WP#/ACC. It creates
internal timing control signals according to the input pins and outputs to the "ADDRESS LATCH AND BUFFER"
to latch the external address pins A0-AM(MSB of address). The internal addresses are output from this block to
the main array and decoders composed of "X-DECODER", "Y-DECODER", "Y-PASS GATE", AND "FLASH AR-
RAY". The X-DECODER decodes the word-lines of the flash array, while the Y-DECODER decodes the bit-lines
of the flash array. The bit lines are electrically connected to the "SENSE AMPLIFIER" and "PGM DATA HV" se-
lectively through the Y-PASS GATES. SENSE AMPLIFIERS are used to read out the contents of the flash mem-
ory, while the "PGM DATA HV" block is used to selectively deliver high power to bit-lines during programming.
The "I/O BUFFER" controls the input and output on the Q0-Q15 pads. During read operation, the I/O BUFFER
receives data from SENSE AMPLIFIERS and drives the output pads accordingly. In the last cycle of program
command, the I/O BUFFER transmits the data on Q0-Q15 to "PROGRAM DATA LATCH", which controls the high
power drivers in "PGM DATA HV" to selectively program the bits in a word or byte according to the user input
pattern.
The "PROGRAM/ERASE HIGH VOLTAGE" block comprises the circuits to generate and deliver the necessary
high voltage to the X-DECODER, FLASH ARRAY, and "PGM DATA HV" blocks. The logic control module com-
prises of the "WRITE STATE MACHINE, WSM", "STATE REGISTER", "COMMAND DATA DECODER", and
"COMMAND DATA LATCH". When the user issues a command by toggling WE#, the command on Q0-Q15 is
latched in the COMMAND DATA LATCH and is decoded by the COMMAND DATA DECODER. The STATE REG-
ISTER receives the command and records the current state of the device. The WSM implements the internal
algorithms for program or erase according to the current command state by controlling each block in the block
diagram.
ARRAY ARCHITECTURE
The main flash memory array can be organized as Word mode (x16). The details of the address ranges and the
corresponding sector addresses are shown in Table 1.
P/N:PM1511
REV. 0.01, AUG. 28, 2009
5
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