MX29GA321EFXCI-70G datasheet, PDF

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MX29GA321EFXCI-70G: DescriptionFlash, 32MX16, 70ns, PBGA64, 10 X 13 MM, 1.20 MM, 1 MM PITCH, ROHS COMPLIANT, MO-216, FBGA-64; Categorystorage storage; File Size2MB，56 Pages; ManufacturerMacronix; Websitehttp://www.macronix.com/en-us/Pages/default.aspx; Environmental Compliance

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MX29GA321EFXCI-70G Overview

Flash, 32MX16, 70ns, PBGA64, 10 X 13 MM, 1.20 MM, 1 MM PITCH, ROHS COMPLIANT, MO-216, FBGA-64

MX29GA321EFXCI-70G Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Macronix
Parts packaging code	BGA
package instruction	TBGA, BGA64,8X8,40
Contacts	64
Reach Compliance Code	unknown
ECCN code	3A991.B.1.A
Maximum access time	70 ns
command user interface	YES
Universal Flash Interface	YES
Data polling	YES
JESD-30 code	R-PBGA-B64
length	13 mm
memory density	536870912 bit
Memory IC Type	FLASH
memory width	16
Number of functions	1
Number of departments/size	64
Number of terminals	64
word count	33554432 words
character code	32000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	32MX16
Package body material	PLASTIC/EPOXY
encapsulated code	TBGA
Encapsulate equivalent code	BGA64,8X8,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE
page size	8 words
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3/3.3 V
Programming voltage	3 V
Certification status	Not Qualified
ready/busy	YES
Maximum seat height	1.2 mm
Department size	32K
Maximum standby current	0.0001 A
Maximum slew rate	0.1 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
switch bit	YES
type	NOR TYPE
width	10 mm

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MX29GA321E C/F

DATASHEET

P/N:PM1511

REV. 0.01, AUG. 28, 2009

MX29GA321E C/F

BLOCK DIAGRAM DESCRIPTION

The block diagram on Page 4 illustrates a simplified architecture of this device. Each block in the block diagram

represents one or more circuit modules in the real chip used to access, erase, program, and read the memory

array.

The "CONTROL INPUT LOGIC" block receives input pins CE#, OE#, WE#, RESET#, and WP#/ACC. It creates

internal timing control signals according to the input pins and outputs to the "ADDRESS LATCH AND BUFFER"

to latch the external address pins A0-AM(MSB of address). The internal addresses are output from this block to

the main array and decoders composed of "X-DECODER", "Y-DECODER", "Y-PASS GATE", AND "FLASH AR-

RAY". The X-DECODER decodes the word-lines of the flash array, while the Y-DECODER decodes the bit-lines

of the flash array. The bit lines are electrically connected to the "SENSE AMPLIFIER" and "PGM DATA HV" se-

lectively through the Y-PASS GATES. SENSE AMPLIFIERS are used to read out the contents of the flash mem-

ory, while the "PGM DATA HV" block is used to selectively deliver high power to bit-lines during programming.

The "I/O BUFFER" controls the input and output on the Q0-Q15 pads. During read operation, the I/O BUFFER

receives data from SENSE AMPLIFIERS and drives the output pads accordingly. In the last cycle of program

command, the I/O BUFFER transmits the data on Q0-Q15 to "PROGRAM DATA LATCH", which controls the high

power drivers in "PGM DATA HV" to selectively program the bits in a word or byte according to the user input

pattern.

The "PROGRAM/ERASE HIGH VOLTAGE" block comprises the circuits to generate and deliver the necessary

high voltage to the X-DECODER, FLASH ARRAY, and "PGM DATA HV" blocks. The logic control module com-

prises of the "WRITE STATE MACHINE, WSM", "STATE REGISTER", "COMMAND DATA DECODER", and

"COMMAND DATA LATCH". When the user issues a command by toggling WE#, the command on Q0-Q15 is

latched in the COMMAND DATA LATCH and is decoded by the COMMAND DATA DECODER. The STATE REG-

ISTER receives the command and records the current state of the device. The WSM implements the internal

algorithms for program or erase according to the current command state by controlling each block in the block

diagram.

ARRAY ARCHITECTURE

The main flash memory array can be organized as Word mode (x16). The details of the address ranges and the

corresponding sector addresses are shown in Table 1.

P/N:PM1511

REV. 0.01, AUG. 28, 2009

MX29GA321EFXCI-70G Related Products

	MX29GA321EFXCI-70G	MX29GA321ECXCI-70G
Description	Flash, 32MX16, 70ns, PBGA64, 10 X 13 MM, 1.20 MM, 1 MM PITCH, ROHS COMPLIANT, MO-216, FBGA-64	Flash, 32MX16, 70ns, PBGA64, 10 X 13 MM, 1.20 MM, 1 MM PITCH, ROHS COMPLIANT, MO-216, FBGA-64
Is it Rohs certified?	conform to	conform to
Maker	Macronix	Macronix
Parts packaging code	BGA	BGA
package instruction	TBGA, BGA64,8X8,40	10 X 13 MM, 1.20 MM, 1 MM PITCH, ROHS COMPLIANT, MO-216, FBGA-64
Contacts	64	64
Reach Compliance Code	unknown	unknown
ECCN code	3A991.B.1.A	3A991.B.1.A
Maximum access time	70 ns	70 ns
command user interface	YES	YES
Universal Flash Interface	YES	YES
Data polling	YES	YES
JESD-30 code	R-PBGA-B64	R-PBGA-B64
length	13 mm	13 mm
memory density	536870912 bit	536870912 bit
Memory IC Type	FLASH	FLASH
memory width	16	16
Number of functions	1	1
Number of departments/size	64	64
Number of terminals	64	64
word count	33554432 words	33554432 words
character code	32000000	32000000
Operating mode	ASYNCHRONOUS	ASYNCHRONOUS
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
organize	32MX16	32MX16
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TBGA	TBGA
Encapsulate equivalent code	BGA64,8X8,40	BGA64,8X8,40
Package shape	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE	GRID ARRAY, THIN PROFILE
page size	8 words	8 words
Parallel/Serial	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED
power supply	3/3.3 V	3/3.3 V
Programming voltage	3 V	3 V
Certification status	Not Qualified	Not Qualified
ready/busy	YES	YES
Maximum seat height	1.2 mm	1.2 mm
Department size	32K	32K
Maximum standby current	0.0001 A	0.0001 A
Maximum slew rate	0.1 mA	0.1 mA
Maximum supply voltage (Vsup)	3.6 V	3.6 V
Minimum supply voltage (Vsup)	2.7 V	2.7 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal form	BALL	BALL
Terminal pitch	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
switch bit	YES	YES
type	NOR TYPE	NOR TYPE
width	10 mm	10 mm

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