EEWORLDEEWORLDEEWORLD

Part Number

Search
 PDF

DM8678CAS/NA+

Description
IC,CHARACTER GENERATOR,TTL,DIP,16PIN,PLASTIC
Categorystorage    storage   
File Size118KB,3 Pages
ManufacturerTexas Instruments
Websitehttp://www.ti.com.cn/
Stay tuned Parametric

DM8678CAS/NA+ Overview

IC,CHARACTER GENERATOR,TTL,DIP,16PIN,PLASTIC

DM8678CAS/NA+ Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerTexas Instruments
package instructionDIP, DIP16,.3
Reach Compliance Codeunknown
Is SamacsysN
JESD-30 codeR-PDIP-T16
JESD-609 codee0
Number of terminals16
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP16,.3
Package shapeRECTANGULAR
Package formIN-LINE
surface mountNO
technologyTTL
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Base Number Matches1
【Qinheng RISC-V core CH582】Evaluation summary
According to the submitted evaluation plan: 1. Unboxing and hardware appreciation 2. Development environment construction and data collection and download 3. Official routine evaluation of the develop...
kit7828 Domestic Chip Exchange
AVR MCU proteus simulation
The source file (c file) cannot be downloaded during simulation. Please help....
加油费 Microchip MCU
Regarding a question about Quartus, please help me with some advice
I'm a newbie and I've just started using Quartus II. I have a question: Can I only compile files with the same name as the top-level entity each time Quartus compiles? What should I do if I want to co...
love2008 Embedded System
PPT of the Analog Electronic Technology Textbook edited by Yang Suxing (full)
PPT of the Analog Electronic Technology Textbook edited by Yang Suxing (full version)...
bqgup Creative Market
A short program for NIOS
I read the program in "Those Things About NIOS", in the serial communication section, I have a little question about the typedef struct { //receiving registerunion{struct{volatile unsigned long int RE...
白丁 FPGA/CPLD
Cache Coherence
1. Configure cacheConfigure L1 Cache:CACHE_L1pSetSize(); CACHE_L1dSetSize(); Configure L2 cache:By default, L2 cache is disabled at startup, and all L2 is SRAM. If DSP/BIOS is enabled, L2 cache is aut...
fish001 DSP and ARM Processors

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2531  436  500  2429  596  51  9  11  49  12 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号