Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10sec) .............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
CC
= +5.0V ±5%, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at T
A
= +25°C.)(Note 1)
PARAMETER
Supply Voltage
Input Voltage High
Input Voltage Low
Input Leakage Current
Active Current
Output Current High
Output Current Low
Input Capacitance
SYMBOL
V
CC
V
IH
V
IL
I
L
I
CC
I
OH
I
OL
C
IN
(Note 2)
(Note 2)
(Note 2)
0V
≤
V
IN
≤
V
CC
V
CC
= 5.25V, period = minimum (Note 3)
V
CC
= 4.75V, V
OH
= 4.0V
V
CC
= 4.75V, V
OL
= 0.5V
T
A
= +25°C (Note 4)
12
5
10
-1
20
CONDITIONS
MIN
4.75
2.2
0.8
1
70
-1
TYP
5.00
MAX
5.25
UNITS
V
V
V
µA
mA
mA
mA
pF
TIMING CHARACTERISTICS
(V
CC
= +5.0V ±5%, T
A
= +25°C, unless otherwise noted.)
PARAMETER
Input Pulse Width
Input-to-Output Delay
(leading edge)
Input-to-Output Delay
(trailing edge)
Power-Up Time
Period
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
SYMBOL
t
WI
t
PLH
t
PHL
t
PU
(Note 5)
3(t
WI
)
CONDITIONS
(Note 5)
(Notes 6, 7, 8)
(Notes 6, 7, 8)
MIN
100% of t
PLH
TYP
MAX
UNITS
ns
ns
ns
100
ms
ns
See Part Number and
Delay Times table
See Part Number and
Delay Times table
Specifications to -40°C are guaranteed by design, not production tested.
All voltages referenced to GND.
Measured with outputs open.
Guaranteed by design.
Pulse width and/or period specifications may be exceeded, but accuracy is application sensitive (i.e., layout, decoupling, etc.).
V
CC
= +5V at +25°C. Typical delays are accurate on both rising and falling edges within ±2ns for delays from 10ns to
60ns, within ±3% for delays from 70ns to 100ns, and within ±5% for delays from 150ns to 200ns.
Note 7:
The
Part Number and Delay Times
table provides typical delays at +25°C with V
CC
= +5V. The delays may shift with tem-
perature and supply variations. The combination of temperature (from +25°C to 0°C, or +25°C to +70°C) and supply varia-
tion (from 5V to 4.75V, or 5V to 5.25V) could produce an additional typical delay of ±1.5ns or ±3%, whichever is greater.
Note 8:
All output delays tend to vary unidirectionally with temperature or supply voltage variations (i.e., if OUT1 slows down, all
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FPGA/CPLD
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