MM74HC540 • MM74HC541 Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer
September 1983
Revised May 2005
MM74HC540 • MM74HC541
Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer
General Description
The MM74HC540 and MM74HC541 3-STATE buffers uti-
lize advanced silicon-gate CMOS technology. They pos-
sess high drive current outputs which enable high speed
operation even when driving large bus capacitances.
These circuits achieve speeds comparable to low power
Schottky devices, while retaining the advantage of CMOS
circuitry, i.e., high noise immunity, and low power consump-
tion. Both devices have a fanout of 15 LS-TTL equivalent
inputs.
The MM74HC540 is an inverting buffer and the
MM74HC541 is a non-inverting buffer. The 3-STATE con-
trol gate operates as a two-input NOR such that if either G1
or G2 are HIGH, all eight outputs are in the high-imped-
ance state.
In order to enhance PC board layout, the MM74HC540 and
MM74HC541 offers a pinout having inputs and outputs on
opposite sides of the package. All inputs are protected from
damage due to static discharge by diodes to V
CC
and
ground.
Features
s
Typical propagation delay: 12 ns
s
3-STATE outputs for connection to system buses
s
Wide power supply range: 2–6V
s
Low quiescent current: 80
P
A maximum (74HC Series)
s
Output current: 6 mA
Ordering Code:
Order Number
MM74HC540WM
MM74HC540SJ
MM74HC540MTC
MM74HC540N
MM74HC541WM
MM74HC541SJ
MM74HC541MTC
MM74HC541N
Package Number
M20B
M20D
MTC20
N20A
M20B
M20D
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
MM74HC541
Top View
MM74HC540
© 2005 Fairchild Semiconductor Corporation
DS005341
www.fairchildsemi.com
MM74HC540 • MM74HC541
Absolute Maximum Ratings
(Note 1)
(Note 2)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
Clamp Diode Current (I
CD
)
DC Output Current, per pin (I
OUT
)
DC V
CC
or GND Current,
per pin (I
CC
)
Storage Temperature Range (T
STG
)
Power Dissipation (P
D
)
(Note 3)
S.O. Package only
Lead Temperature (T
L
)
(Soldering 10 seconds)
260
q
C
(Note 4)
V
CC
2.0V
4.5V
6.0V
V
IL
Maximum LOW Level
Input Voltage
V
OH
Minimum HIGH Level
Output Voltage
V
IN
V
IH
or V
IL
2.0V
4.5V
6.0V
V
IN
V
IH
or V
IL
4.5V
6.0V
2.0V
4.5V
6.0V
V
IN
V
IH
or V
IL
4.5V
6.0V
6.0V
|I
OUT
|
d
6.0 mA
|I
OUT
|
d
7.8 mA
I
IN
Maximum Input
Current
I
OZ
Maximum 3-STATE
Output Leakage
Current
I
CC
Maximum Quiescent
Supply Current
V
IN
I
OUT
V
CC
or GND
0
P
A
6.0V
V
IN
V
OUT
V
IH
or V
IL
, G
V
CC
or GND
V
IH
6.0V
V
IN
V
CC
or GND
|I
OUT
|
d
6.0 mA
|I
OUT
|
d
7.8 mA
V
OL
Maximum LOW Level
Output Voltage
V
IN
V
IH
or V
IL
|I
OUT
|
d
20
P
A
2.0V
4.5V
6.0V
|I
OUT
|
d
20
P
A
Recommended Operating
Conditions
Min
Supply Voltage (V
CC
)
DC Input or Output Voltage
(V
IN
, V
OUT
)
Operating Temperature Range (T
A
)
Input Rise or Fall Times
(t
r
, t
f
) V
CC
V
CC
V
CC
2.0V
4.5V
6.0V
0
V
CC
V
2
Max
6
Units
V
0.5 to
7.0V
1.5 to V
CC
1.5V
0.5 to V
CC
0.5V
r
20 mA
r
35 mA
r
70 mA
65
q
C to
150
q
C
600 mW
500 mW
40
85
1000
500
400
q
C
ns
ns
ns
Note 1:
Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2:
Unless otherwise specified all voltages are referenced to ground.
Note 3:
Power Dissipation temperature derating — plastic “N” package:
12 mW/
q
C from 65
q
C to 85
q
C.
DC Electrical Characteristics
Symbol
V
IH
Parameter
Minimum HIGH Level
Input Voltage
Conditions
T
A
Typ
25
q
C
1.5
3.15
4.2
0.5
1.35
1.8
T
A
40 to 85
q
C T
A
55 to 125
q
C
Guaranteed Limits
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
Units
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
2.0
4.5
6.0
4.2
5.7
0
0
0
0.2
0.2
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
r
0.1
r
0.5
r
1.0
r
5
r
1.0
r
10
P
A
P
A
8.0
80
160
P
A
Note 4:
For a power supply of 5V
r
10% the worst case output voltages (V
OH
, and V
OL
) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case V
IH
and V
IL
occur at V
CC
5.5V and 4.5V respectively. (The V
IH
value at 5.5V is 3.85V.) The worst case leakage cur-
rent (I
IN
, I
CC
, and I
OZ
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
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2
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