Preliminary v1.7
Actel Fusion Mixed-Signal FPGAs
Family with Optional ARM
®
Support
Features and Benefits
High-Performance Reprogrammable Flash
Technology
•
•
•
•
Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process
Nonvolatile, Retains Program when Powered Off
Live at Power-Up (LAPU) Single-Chip Solution
350 MHz System Performance
– Frequency: Input 1.5–350 MHz, Output 0.75–350 MHz
®
Low Power Consumption
• Single 3.3 V Power Supply with On-Chip 1.5 V Regulator
• Sleep and Standby Low Power Modes
In-System Programming (ISP) and Security
• Secure ISP with 128-Bit AES via JTAG
• FlashLock
®
to Secure FPGA Contents
Embedded Flash Memory
• User Flash Memory – 2 Mbits to 8 Mbits
– Configurable 8-, 16-, or 32-Bit Datapath
– 10 ns Access in Read-Ahead Mode
• 1 kbit of Additional FlashROM
Advanced Digital I/O
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages – Up to 5 Banks per Chip
• Single-Ended
I/O
Standards:
LVTTL,
LVCMOS
3.3 V / 2.5 V /1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and
LVCMOS 2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS
– Built-In I/O Registers
– 700 Mbps DDR Operation
• Hot-Swappable I/Os
• Programmable Output Slew Rate, Drive Strength, and Weak
Pull-Up/Down Resistor
• Pin-Compatible Packages across the Fusion Family
Integrated A/D Converter (ADC) and Analog I/O
•
•
•
•
•
•
Up to 12-Bit Resolution and up to 600 ksps
Internal 2.56 V or External Reference Voltage
ADC: Up to 30 Scalable Analog Input Channels
High-Voltage Input Tolerance: –10.5 V to +12 V
Current Monitor and Temperature Monitor Blocks
Up to 10 MOSFET Gate Driver Outputs
– P- and N-Channel Power MOSFET Support
– Programmable 1, 3, 10, 30 µA and 20 mA Drive Strengths
• ADC Accuracy is Better than 1%
SRAMs and FIFOs
• Variable-Aspect-Ratio 4,608-Bit SRAM Blocks (×1, ×2, ×4, ×9,
and ×18 organizations available)
• True Dual-Port SRAM (except ×18)
• Programmable Embedded FIFO Control Logic
On-Chip Clocking Support
•
•
•
•
Internal 100 MHz RC Oscillator (accurate to 1%)
Crystal Oscillator Support (32 kHz to 20 MHz)
Programmable Real-Time Counter (RTC)
6 Clock Conditioning Circuits (CCCs) with 1 or 2 Integrated
PLLs
– Phase Shift, Multiply/Divide, and Delay Capabilities
Soft ARM7™ Core Support in M7 and M1 Fusion Devices
• ARM Cortex™-M1 (without debug), CoreMP7Sd (with
debug) and CoreMP7S (without debug)
Fusion Family
Fusion Devices
ARM-Enabled
Fusion Devices
CoreMP7
1
AFS090
Cortex-M1
2
System Gates
Tiles (D-flip-flops)
Secure (AES) ISP
90,000
2,304
Yes
1
18
1
2M
1k
6
27
5
15
5
4
75
20
AFS250
M1AFS250
250,000
6,144
Yes
1
18
1
2M
1k
8
36
6
18
6
4
114
24
AFS600
M7AFS600
M1AFS600
600,000
13,824
Yes
2
18
2
4M
1k
24
108
10
30
10
5
172
40
AFS1500
M1AFS1500
1,500,000
38,400
Yes
2
18
4
8M
1k
60
270
10
30
10
5
252
40
General
Information
PLLs
Globals
Flash Memory Blocks (2 Mbits)
Total Flash Memory Bits
Memory
FlashROM Bits
RAM Blocks (4,608 bits)
RAM kbits
Analog Quads
Analog Input Channels
Gate Driver Outputs
I/O Banks (+ JTAG)
Maximum Digital I/Os
Analog I/Os
Analog and I/Os
Notes:
1. Refer to the
CoreMP7
datasheet for more information.
2. Refer to the
Cortex-M1
product brief for more information.
October 2008
© 2009 Actel Corporation
I
Actel Fusion Mixed-Signal FPGAs
Fusion Device Architecture Overview
Bank 0
Bank 1
CCC
SRAM Block
4,608-Bit Dual-Port SRAM
or FIFO Block
OSC
I/Os
CCC/PLL
VersaTile
Bank 2
Bank 4
ISP AES
Decryption
User Nonvolatile
FlashROM
Charge Pumps
SRAM Block
4,608-Bit Dual-Port SRAM
or FIFO Block
Flash Memory Blocks
ADC
Flash Memory Blocks
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
CCC
Bank 3
Figure 1-1 •
Fusion Device Architecture Overview (AFS600)
Package I/Os: Single-/Double-Ended (Analog)
Fusion Devices
CoreMP7
ARM-Enabled Devices
QN108
QN180
PQ208
FG256
FG484
FG676
75/22 (20)
Cortex-M1
37/9 (16)
60/16 (20)
65/15 (24)
93/26 (24)
114/37 (24)
95/46 (40)
119/58 (40)
172/86 (40)
119/58 (40)
223/109 (40)
252/126 (40)
M1AFS250
AFS090
AFS250
AFS600
M7AFS600
M1AFS600
M1AFS1500
AFS1500
Note:
All devices in the same package are pin compatible with the exception of the PQ208 package (AFS250 and AFS600).
II
P r el im in ar y v 1 .7
Actel Fusion Mixed-Signal FPGAs
Product Ordering Codes
M7AFS600
_
1
FG
G
256
I
Application (ambient temperature range)
Blank = Commercial (0 to +70°C)
I = Industrial (–40 to +85°C)
PP = Pre-Production
ES = Engineering Silicon (room temperature only)
Package Lead Count
Lead-Free Packaging Options
Blank = Standard Packaging
G = RoHS-Compliant (green) Packaging
Package Type
QN = Quad Flat No Lead (0.5 mm pitch)
PQ = Plastic Quad Flat Pack (0.5 mm pitch)
FG = Fine Pitch Ball Grid Array (1.0 mm pitch)
Speed Grade
F = 20% Slower than Standard
Blank = Standard
1 = 15% Faster than Standard
2 = 25% Faster than Standard
Part Number
Fusion Devices
AFS090 = 90,000 System Gates
AFS250 = 250,000 System Gates
AFS600 = 600,000 System Gates
AFS1500 = 1,500,000 System Gates
ARM-Enabled Fusion Devices
M7AFS600
M1AFS250
M1AFS600
M1AFS1500
=
=
=
=
600,000 System Gates
250,000 System Gates
600,000 System Gates
1,500,000 System Gates
Notes:
1. DC and switching characteristics for –F speed grade targets are based only on simulation. The characteristics provided for
the –F speed grade are subject to change after establishing FPGA specifications. Some restrictions might be added and
will be reflected in future revisions of this document. The –F speed grade is only supported in the commercial
temperature range.
2. Quad Flat No Lead packages are only offered as RoHS compliant, QNG.
P re li m i n a ry v 1 .7
III
Actel Fusion Mixed-Signal FPGAs
Temperature Grade Offerings
Fusion Devices
CoreMP7
ARM-Enabled Devices
QN108
QN180
PQ208
FG256
FG484
FG676
Cortex-M1
C, I
C, I
–
C, I
–
–
M1AFS250
–
C, I
C, I
C, I
–
–
AFS090
AFS250
AFS600
M7AFS600
M1AFS600
–
–
C, I
C, I
C, I
–
M1AFS1500
–
–
–
C, I
C, I
C, I
AFS1500
Notes:
1. C = Commercial Temperature Range: 0°C to 70°C Ambient
2. I = Industrial Temperature Range: –40°C to 85°C Ambient
Speed Grade and Temperature Grade Matrix
–F
1
C
2
I
3
Std.
–1
–2
✓
–
✓
✓
✓
✓
✓
✓
Notes:
1. DC and switching characteristics for –F speed grade targets are based only on simulation. The characteristics provided
for the –F speed grade are subject to change after establishing FPGA specifications. Some restrictions might be added
and will be reflected in future revisions of this document. The –F speed grade is only supported in the commercial
temperature range.
2. C = Commercial Temperature Range: 0°C to 70°C Ambient
3. I = Industrial Temperature Range: –40°C to 85°C Ambient
Contact your local Actel representative for device availability (http://www.actel.com/contact/offices/index.html).
IV
P r el im in ar y v 1 .7
1 – Fusion Device Family Overview
Introduction
The Actel Fusion
®
mixed-signal FPGA satisfies the demand from system architects for a device that
simplifies design and unleashes their creativity. As the world’s first mixed-signal programmable
logic family, Fusion integrates mixed-signal analog, flash memory, and FPGA fabric in a monolithic
device. Actel Fusion devices enable designers to quickly move from concept to completed design
and then deliver feature-rich systems to market. This new technology takes advantage of the
unique properties of Actel flash-based FPGAs, including a high-isolation, triple-well process and the
ability to support high-voltage transistors to meet the demanding requirements of mixed-signal
system design.
Actel Fusion mixed-signal FPGAs bring the benefits of programmable logic to many application
areas, including power management, smart battery charging, clock generation and management,
and motor control. Until now, these applications have only been implemented with costly and
space-consuming discrete analog components or mixed-signal ASIC solutions. Actel Fusion mixed-
signal FPGAs present new capabilities for system development by allowing designers to integrate a
wide range of functionality into a single device, while at the same time offering the flexibility of
upgrades late in the manufacturing process or after the device is in the field. Actel Fusion devices
provide an excellent alternative to costly and time-consuming mixed-signal ASIC designs. In
addition, when used in conjunction with the Actel or ARM-based soft MCU core, Actel Fusion
technology represents the definitive mixed-signal FPGA platform.
Flash-based Fusion devices are live at power-up. As soon as system power is applied and within
normal operating specifications, Fusion devices are working. Fusion devices have a 128-bit flash-
based lock and industry-leading AES decryption, used to secure programmed intellectual property
(IP) and configuration data. Actel Fusion devices are the most comprehensive single-chip analog
and digital programmable logic solution available today.
To support this new ground-breaking technology, Actel has developed a series of major tool
innovations to help maximize designer productivity. Implemented as extensions to the popular
Actel Libero
®
Integrated Design Environment (IDE), these new tools allow designers to easily
instantiate and configure peripherals within a design, establish links between peripherals, create
or import building blocks or reference designs, and perform hardware verification. This tool suite
will also add comprehensive hardware/software debug capability as well as a suite of utilities to
simplify development of embedded soft-processor-based solutions.
General Description
The Actel Fusion family, based on the highly successful ProASIC
®
3 and ProASIC3E Flash FPGA
architecture, has been designed as a high-performance, programmable, mixed-signal platform. By
combining an advanced flash FPGA core with flash memory blocks and analog peripherals, Fusion
devices dramatically simplify system design and, as a result, dramatically reduce overall system cost
and board space.
The state-of-the-art flash memory technology offers high-density integrated flash memory blocks,
enabling savings in cost, power, and board area relative to external flash solutions, while providing
increased flexibility and performance. The flash memory blocks and integrated analog peripherals
enable true mixed-mode programmable logic designs. Two examples are using an on-chip soft
processor to implement a fully functional Flash MCU and using high-speed FPGA logic to offer
system and power supervisory capabilities. Live at power-up and capable of operating from a single
3.3 V supply, the Fusion family is ideally suited for system management and control applications.
The devices in the Fusion family are categorized by FPGA core density. Each family member
contains many peripherals, including flash memory blocks, an analog-to-digital-converter (ADC),
high-drive outputs, both RC and crystal oscillators, and a real-time counter (RTC). This provides the
Pr e li m i n a ry v1 . 7
1-1
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