®
74LVX374
LOW VOLTAGE OCTAL D-TYPE FLIP FLOP
(3-STATE NON INV.) WITH 5V TOLERANT INPUTS
s
s
s
s
s
s
s
s
s
s
s
HIGH SPEED:
f
MAX
= 160 MHz (TYP.) at V
CC
= 3.3V
5V TOLERANT INPUTS
POWER-DOWN PROTECTION ON INPUTS
INPUT VOLTAGE LEVEL:
V
IL
= 0.8V, V
IH
= 2V at V
CC
= 3V
LOW POWER DISSIPATION:
I
CC
= 4
µA
(MAX.) at T
A
= 25
o
C
LOW NOISE:
V
OLP
= 0.3 V (TYP.) at V
CC
= 3.3V
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 374
IMPROVED LATCH-UP IMMUNITY
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74LVX374M
74LVX374T
outputs will be set to the logic state that were
setup at the D inputs.
While the (OE) input is low, the 8 outputs will be
in a normal state (high or low logic level) and
while high level the outputs will be in a high
impedance state.
The output control does not affect the internal
operation of flip flops; that is, the old data can be
retained or the new data can be entered even
while the outputs are off.
It has better speed performance at 3.3V than 5V
LSTTL family combined with the true CMOS low
power consumption.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
DESCRIPTION
The LVX374 is a low voltage CMOS OCTAL
D-TYPE FLIP FLOP with 3 STATE OUTPUT
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power and low noise
applications.
This 8 bit D-Type flip-flop is controlled by a clock
input (CK) and an output enable input (OE).
On the positive transition of the clock, the Q
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 1999
1/10
74LVX374
AC ELECTRICAL CHARACTERISTICS
(Input t
r
= t
f
=3 ns)
Symb ol
Parameter
T est Con ditio n
V
CC
C
L
(V)
(p F)
2.7
2.7
3.3
(*)
3.3
(*)
2.7
2.7
3.3
(*)
3.3
(*)
2.7
3.3
2.7
(*)
t
PLH
t
PHL
Propagation Delay Time
CK to Q
15
50
15
50
15
50
15
50
15
50
15
50
15
50
15
50
15
50
15
50
50
50
Valu e
T
A
= 25 C
-40 to
Min. T yp. Max. Min.
8.5
16.3
1.0
11.0 19.8
1.0
o
Un it
85 C
Max.
19.5
23.0
12.5
16.0
17.5
21.0
11.0
14.5
22.0
15.0
8.0
5.5
6.5
4.5
2.0
2.0
o
ns
t
PZL
t
PZH
Output Enable Time
R
L
= 1 k
Ω
t
PLZ
t
PHZ
t
w
t
s
t
h
f
MAX
Output Disable Time
Clock pulse Width,
HIGH or LOW
Setup Time D to CK
HIGH or LOW
Hold Time D to CK
HIGH or LOW
Maximum Clock
Frequency
R
L
= 1 k
Ω
6.7
9.2
7.6
10.1
5.9
8.4
11.5
9.6
10.6
14.1
14.5
18.0
9.3
12.8
18.5
13.2
7.5
5.0
6.5
4.5
2.0
2.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
ns
ns
ns
ns
ns
3.3
(*)
2.7
3.3
(*)
2.7
3.3
(*)
2.7
2.7
3.3
(*)
3.3
2.7
3.3
(*)
60
45
100
60
115
60
160
95
0.5
0.5
1.0
1.0
50
40
85
55
1.5
1.5
MHz
t
OSLH
t
OSHL
Output to Output Skew
Time (note 1, 2)
ns
(*)
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any twooutputs of the same device switching in the
same direction, either HIGH or LOW
2) Parameter guaranteed by design
CAPACITIVE CHARACTERISTICS
Symb ol
Parameter
V
CC
(V)
C
IN
C
OUT
C
PD
Input Capacitance
Output Capacitance
Power Dissipation
Capacitance (note 1)
3.3
3.3
3.3
f
IN
= 10 MHz
Test Co nditions
o
Valu e
T
A
= 25 C
Min.
T yp.
4
6
32
Max.
10
-40 to 85 C
Min.
Max.
10
o
Un it
pF
pF
pF
1) C
PD
isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto
Test Circuit).Average operting current can be obtained by the following equation. I
CC
(opr) = C
PD
•
V
CC
•
f
IN
+ I
CC
/8(per circuit)
5/10
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