TIBPAL20L8-15C, TIBPAL20R4-15C, TIBPAL20R6-15C, TIBPAL20R8-15C
TIBPAL20L8-20M, TIBPAL20R4-20M, TIBPAL20R6-20M, TIBPAL20R8-20M
HIGH-PERFORMANCE
IMPACT
™
PAL
®
CIRCUITS
•
•
•
•
•
•
•
High-Performance: f
max
(w/o feedback)
TIBPAL20R’ -15C Series . . . 45 MHz
TIBPAL20R’ -20M Series . . . 41.6 MHz
High-Performance . . . 45 MHz Min
Reduced I
CC
of 180 mA Max
Functionally Equivalent, but Faster Than
PAL20L8, PAL20R4, PAL20R6, PAL20R8
Power-Up Clear on Registered Devices (All
Register Outputs are Set Low, but Voltage
Levels at the Output Pins Go High)
Preload Capability on Output Registers
Simplifies Testing
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
DEVICE
PAL20L8
PAL20R4
PAL20R6
PAL20R8
I
INPUTS
14
12
12
12
3-STATE
O OUTPUTS
2
0
0
0
REGISTERED
Q OUTPUTS
0
4 (3-state buffers)
6 (3-state buffers)
8 (3-state buffers)
I/O
PORT
S
6
4
2
0
SRPS021 – D2920, JUNE 1986 – REVISED AUGUST 1989
TIBPAL20L8’
C SUFFIX . . . JT OR NT PACKAGE
M SUFFIX . . . JT OR W PACKAGE
(TOP VIEW)
I
I
I
I
I
I
I
I
I
I
I
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
I
O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
TIBPAL20L8’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
description
These programmable array logic devices feature
high speed and functional equivalency when
compared with currently available devices. These
IMPACT™ circuits combine the latest Advanced
Low-Power Schottky technology with proven
titanium-tungsten fuses to provide reliable,
high-performance substitutes for conventional
TTL logic. Their easy programmability allows for
quick design of custom functions and typically
results in a more compact circuit board. In
addition, chip carriers are available for futher
reduction in board space.
I
I
I
NC
I
I
I
5
6
7
8
9
10
I
I
I
NC
V
CC
I
O
4
3 2 1 28 27 26
25
24
23
22
21
20
11
19
12 13 14 15 16 17 18
I/O
I/O
I/O
NC
I/O
I/O
I/O
NC
–
No internal connection
Pin assignments in operating mode
Extra circuitry has been provided to allow loading of each register asynchronously to either a high or low state.
This feature simplifies testing because the registers can be set to an initial state prior to executing the test
sequence.
The TIBPAL20’ C series is characterized from 0°C to 75°C. The TIBPAL20’ M series is characterized for
operation over the full military temperature range of –55°C to 125°C.
These devices are covered by U.S. Patent 4,410,987.
IMPACT is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Advanced Micro Devices Inc.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily
include testing of all parameters.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
I
I
GND
NC
I
I
O
Copyright
©
1989, Texas Instruments Incorporated
1
SRPS021 – D2920, JUNE 1986 – REVISED AUGUST 1989
TIBPAL20R4-15C, TIBPAL20R6-15C, TIBPAL20R8-15C
TIBPAL20R4-20M, TIBPAL20R6-20M, TIBPAL20R8-20M
HIGH-PERFORMANCE
IMPACT
™
PAL
®
CIRCUITS
TIBPAL20R4’
C SUFFIX . . . JT OR NT PACKAGE
M SUFFIX . . . JT OR W PACKAGE
(TOP VIEW)
CLK
I
I
I
I
I
I
I
I
I
I
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I
I/O
I/O
Q
Q
Q
Q
I/O
I/O
I
OE
TIBPAL20R4’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
VCC
I
I/O
I/O
Q
Q
NC
Q
Q
I/O
VCC
I
I/O
Q
Q
Q
NC
Q
Q
Q
VCC
I
Q
Q
Q
Q
NC
Q
Q
Q
OE
I
Q
OE
I
I/O
OE
I
I/O
I
I
CLK
NC
I
I
I
NC
I
I
I
I
I
I
NC
I
I
I
I
I
I
NC
I
I
I
NC
POST OFFICE BOX 655303
4 3 2 1 28 27 26
5
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
I
I
GND
NC
TIBPAL20R6’
C SUFFIX . . . JT OR NT PACKAGE
M SUFFIX . . . JT OR W PACKAGE
(TOP VIEW)
CLK
I
I
I
I
I
I
I
I
I
I
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I
I/O
Q
Q
Q
Q
Q
Q
I/O
I
OE
TIBPAL20R6’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
I
I
CLK
NC
4 3 2 1 28 27 26
5
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
I
I
GND
NC
TIBPAL20R8’
C SUFFIX . . . JT OR NT PACKAGE
M SUFFIX . . . JT OR W PACKAGE
(TOP VIEW)
CLK
I
I
I
I
I
I
I
I
I
I
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I
Q
Q
Q
Q
Q
Q
Q
Q
I
OE
TIBPAL20R8’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
I
I
CLK
NC
4 3 2 1 28 27 26
5
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
I
I
GND
NC
Pin assignments in operating mode
–
No internal connection
2
•
DALLAS, TEXAS 75265
京公网安备 11010802033920号
EEWORLD
