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BLM21PG600SN1J

Description
Ferrite Chip, 1 Function(s), 3A, EIA STD PACKAGE SIZE 0805, 2 PIN
CategoryAnalog mixed-signal IC    filter   
File Size472KB,62 Pages
ManufacturerMurata
Websitehttps://www.murata.com
Environmental Compliance  
Download Datasheet Parametric View All

BLM21PG600SN1J Overview

Ferrite Chip, 1 Function(s), 3A, EIA STD PACKAGE SIZE 0805, 2 PIN

BLM21PG600SN1J Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
package instruction0805
Reach Compliance Codecompliant
ECCN codeEAR99
Samacsys Confidence2
Samacsys StatusReleased
Samacsys PartID4059571
Samacsys Pin Count2
Samacsys Part CategoryFilter
Samacsys Package CategoryOther
Samacsys Footprint NameBLM21_3 L=2.0 W=1.25 T=0.85
Samacsys Released Date2019-10-10 10:28:45
Is SamacsysN
Other featuresMONOLITHIC TYPE
shell code0805
structureChip Bead
Maximum DC resistance0.025 Ω
filter typeFERRITE CHIP
maximum frequency100 MHz
minimum frequency100 MHz
high0.85 mm
JESD-609 codee3
length2 mm
MaterialFerrite
Installation typeSURFACE MOUNT
Number of functions1
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Output impedance60 OHM Ω
method of packingTAPE AND REEL
physical sizeL2.0XB1.25XH0.85 (mm)/L0.079XB0.049XH0.033 (inch)
Rated current3 A
Terminal surfaceTin (Sn)
width1.25 mm
Base Number Matches1
MAX 7000
®
Programmable Logic
Device Family
Data Sheet
March 2001, ver. 6.1
Features...
s
s
s
s
s
s
s
High-performance, EEPROM-based programmable logic devices
(PLDs) based on second-generation MAX
®
architecture
5.0-V in-system programmability (ISP) through the built-in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in
MAX 7000S devices
ISP circuitry compatible with IEEE Std. 1532
Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S
devices
Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S
devices with 128 or more macrocells
Complete EPLD family with logic densities ranging from 600 to
5,000 usable gates (see
Tables 1
and
2)
5-ns pin-to-pin logic delays with up to 175.4-MHz counter
frequencies (including interconnect)
PCI-compliant devices available
f
For information on in-system programmable 3.3-V MAX 7000A or 2.5-V
MAX 7000B devices, see the
MAX 7000A Programmable Logic Device Family
Data Sheet
or the
MAX 7000B Programmable Logic Device Family Data
Sheet.
Table 1. MAX 7000 Device Features
Feature
Usable
gates
Macrocells
Logic array
blocks
Maximum
user I/O pins
t
PD
(ns)
t
SU
(ns)
t
FSU
(ns)
t
CO1
(ns)
f
CNT
(MHz)
EPM7032
600
32
2
36
6
5
2.5
4
151.5
EPM7064
1,250
64
4
68
6
5
2.5
4
151.5
EPM7096
1,800
96
6
76
7.5
6
3
4.5
125.0
EPM7128E
2,500
128
8
100
7.5
6
3
4.5
125.0
EPM7160E
3,200
160
10
104
10
7
3
5
100.0
EPM7192E
3,750
192
12
124
12
7
3
6
90.9
EPM7256E
5,000
256
16
164
12
7
3
6
90.9
Altera Corporation
A-DS-M7000-06.1
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