HD74AC194
4-bit Bidirectional Unviersal Shift Register
ADE-205-379 (Z)
1st. Edition
Sep. 2000
Description
This bidirectional shift register is designed to incorporate virtually all of the features a system designer may
want in a shift register. It features parallel inputs, parallel outputs, right shift and left shift serial inputs,
operating mode control inputs, and a direct overriding clear line. The register has four destinct modes of
operation: parallel (broadside) load, shift right (in the direction Q
0
toward Q
3
); shift left; inhibit clock (do
nothing).
Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode
control inputs, S
0
and S
1
, high. The data are loaded into their respective flip-flops and appear at the output
after the positive transition of the clock input. During loading, serial data flow is inhibited. Shift right is
accomplished synchronously with the rising edge of the clock pulse when S
0
is high and S
1
is low. Serial
date for this mode is entered at the shift right data input. When S
0
is low and S
1
is high, data shifts left
synchronously and new data is entered at the shifts left serial input. Clocking of the flip-flops is inhibited
when both mode control inputs are low. The mode control inputs should be changed only when the clock
input is high.
Features
•
Asynchronous Master Reset
•
Hole (Do Nothing) Mode
•
Outputs Source/Sink 24 mA
HD74AC194
Pin Arrangement
MR
1
D
SR
2
P
0
3
P
1
4
P
2
5
P
3
6
D
SL
7
GND 8
(Top view)
16 V
CC
15 Q
0
14 Q
1
13 Q
2
12 Q
3
11 CP
10 S
1
9 S
0
Logic Symbol
D
SR
P
0
S
0
S
1
CP
MR
Q
0
P
1
P
2
P
3
D
SL
Q
1
Q
2
Q
3
Pin Names
S
0
, S
1
P
0
to P
3
D
SR
D
SL
CP
MR
Q
0
to Q
3
Mode Control Inputs
Parallel Data Inputs
Serial Data Input (Shift Right)
Serial Data Input (Shift Left)
Clock Pulse Input (Active Rising Edge)
Asynchronous Master Reset Input (Active LOW)
Parallel Outputs
2
HD74AC194
Timing Diagram
CP
Mode
Control
Inputs
S
1
MR
Parallel
Data
Inputs
D
SH
D
SL
P
0
Parallel
Data
Inputs
P
2
P
3
Q
0
Outputs
Q
1
Q
2
Q
3
Shift Right
Clear
Load
Shift Left
Inhibit
Clear
H
L
P
1
H
L
S
0
DC Characteristics
(unless otherwise specified)
Item
Maximum quiescent supply current
Maximum quiescent supply current
Symbol
I
CC
I
CC
Max
80
8.0
Unit
µA
µA
Condition
V
IN
= V
CC
or ground, V
CC
= 5.5 V,
Ta = Worst case
V
IN
= V
CC
or ground, V
CC
= 5.5 V,
Ta = 25°C
4
HD74AC194
AC Characteristics: HD74AC194
Ta = +25°C
C
L
= 50 pF
Item
Maximum clock
frequency
Propagation delay
CP to Q
n
Propagation delay
CP to Q
n
Propagation delay
MR
to Q
n
Note:
t
PHL
t
PHL
t
PLH
Symbol
f
max
V
CC
(V)*
1
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
Min
75
100
1.0
1.0
1.0
1.0
1.0
1.0
Typ
—
—
—
—
—
—
—
—
13.0
10.0
13.0
10.0
10.5
8.0
Max
Ta = –40°C to +85°C
C
L
= 50 pF
Min
65
85
1.0
1.0
1.0
1.0
1.0
1.0
15.0
11.5
15.0
11.5
12.5
9.0
ns
ns
ns
Max
Unit
MHz
1. Voltage Range 3.3 is 3.3 V
±
0.3 V
Voltage Range 5.0 is 5.0 V
±
0.5 V
AC Operating Requirements: HD74AC194
Ta = +25°C
C
L
= 50 pF
Item
Setup time, HIGH or LOW
Pn or D
SR
or D
SL
to CP
Hold time, HIGH or LOW
Pn or D
SR
or D
SL
to CP
Setup time, HIGH or LOW
S
n
to CP
Hold time, HIGH or LOW
S
n
to CP
Recovery time
MR
to CP
Pulse width
t
w
t
rec
t
h
t
su
t
h
Symbol
t
su
V
CC
(V)*
1
Typ
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
Note:
1. Voltage Range 3.3 is 3.3 V
±
0.3 V
Voltage Range 5.0 is 5.0 V
±
0.5 V
—
—
—
—
—
—
—
—
—
—
—
—
Ta = –40°C
to +85°C
C
L
= 50 pF
Guaranteed Minimum
5.5
4.0
2.0
1.5
6.0
4.5
0.0
0.0
0.5
0.5
5.5
4.5
7.0
5.0
3.0
2.0
7.5
5.5
0.0
0.0
0.5
0.5
7.0
5.0
ns
ns
ns
ns
ns
Unit
ns
5
Buy&Sell
京公网安备 11010802033920号
EEWORLD
