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MC74F195J

Description
4-BIT PARALLEL ACCESS SHIFT REGISTER
Categorylogic    logic   
File Size39KB,4 Pages
ManufacturerMotorola ( NXP )
Websitehttps://www.nxp.com
Download Datasheet Parametric Compare View All

MC74F195J Overview

4-BIT PARALLEL ACCESS SHIFT REGISTER

MC74F195J Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerMotorola ( NXP )
Parts packaging codeDIP
package instructionDIP, DIP16,.3
Contacts16
Reach Compliance Codeunknow
Other featuresCOMPLEMENTARY SERIAL SHIFT RIGHT OUTPUT; J AND KBAR SERIAL INPUT
Counting directionRIGHT
seriesF/FAST
JESD-30 codeR-GDIP-T16
JESD-609 codee0
length19.3 mm
Load capacitance (CL)50 pF
Logic integrated circuit typePARALLEL IN PARALLEL OUT
Maximum Frequency@Nom-Su90000000 Hz
Number of digits4
Number of functions1
Number of terminals16
Maximum operating temperature70 °C
Minimum operating temperature
Output polarityTRUE
Package body materialCERAMIC, GLASS-SEALED
encapsulated codeDIP
Encapsulate equivalent codeDIP16,.3
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Maximum supply current (ICC)38 mA
propagation delay (tpd)9 ns
Certification statusNot Qualified
Maximum seat height4.19 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyTTL
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Trigger typePOSITIVE EDGE
width7.62 mm
minfmax90 MHz
MC74F195
4-BIT PARALLEL
ACCESS SHIFT REGISTER
The functional characteristics of the MC74F195 4-Bit Parallel Access Shift
Register are indicated in the Logic Diagram and Function Table. The device
is useful in a wide variety of shifting, counting, and storage applications. It per-
forms serial, parallel, serial-to-parallel, or parallel-to-serial data transfers at
very high speeds.
The MC74F195 operates in two primary modes, shift right (Q0-Q1) and par-
allel load, which are controlled by the state of the Parallel Enable (PE) input.
Serial data enters the first flip-flop (Q0) via the J and K inputs when the PE
input is HIGH, and is shifted 1 bit in the direction Q0-Q1-Q2-Q3 following each
LOW-to-HIGH clock transition. The J and K inputs provide the flexibility of the
JK type input is made for special applications, and by tying the two pins togeth-
er the simple D-type input is made for general applications. The device ap-
pears as four common clocked D flip-flops when the PE input is LOW. After
the LOW-to-HIGH clock transition, data on the parallel inputs (D0-D3) is trans-
ferred to the respective Q0-Q3 outputs. Shift left operation (Q3-Q2) can be
achieved by tying the Qn outputs to the Dn-1 inputs and holding the PE input
LOW.
All parallel and serial data transfers are synchronous, occurring after each
LOW-to-HIGH clock transition. The MC74F195 utilizes edge-triggering;
therefore, there is no restriction on the activity of the J, K, Dn, and PE inputs
for logic operation, other than the setup and hold time requirements.
A LOW on the asynchronous Master Reset (MR) input sets all Q outputs
LOW, independent of any other input condition.
Shift Right and Parallel Load Capability
J-K (D-Type) Inputs to First Stage
Complement Output from Last Stage
Asynchronous Master Reset
4-BIT PARALLEL
ACCESS SHIFT REGISTER
FAST™ SCHOTTKY TTL
J SUFFIX
CERAMIC
CASE 620-09
16
1
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
CONNECTION DIAGRAM DIP
VCC
16
Q0
15
Q1
14
Q2
13
Q3
12
Q3
11
CP
10
PE
9
MC74FXXXJ
MC74FXXXN
MC74FXXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
9
2
1
MR
2
J
3
K
4
D0
5
D1
6
D2
7
D3
8
GND
10
3
J
4 5
6
7
PE D0 D1 D2 D3
11
Q3
CP
K
MR Q0 Q1 Q2 Q3
1 15 14 13 12
VCC = PIN 16
GND = PIN 8
FAST AND LS TTL DATA
4-104

MC74F195J Related Products

MC74F195J MC74F195N MC74F195 MC74F195D
Description 4-BIT PARALLEL ACCESS SHIFT REGISTER 4-BIT PARALLEL ACCESS SHIFT REGISTER 4-BIT PARALLEL ACCESS SHIFT REGISTER 4-BIT PARALLEL ACCESS SHIFT REGISTER
Is it Rohs certified? incompatible incompatible - incompatible
Maker Motorola ( NXP ) Motorola ( NXP ) - Motorola ( NXP )
package instruction DIP, DIP16,.3 DIP, DIP16,.3 - SOP, SOP16,.25
Reach Compliance Code unknow unknow - unknow
Other features COMPLEMENTARY SERIAL SHIFT RIGHT OUTPUT; J AND KBAR SERIAL INPUT COMPLEMENTARY SERIAL SHIFT RIGHT OUTPUT; J AND KBAR SERIAL INPUT - COMPLEMENTARY SERIAL SHIFT RIGHT OUTPUT; J AND KBAR SERIAL INPUT
Counting direction RIGHT RIGHT - RIGHT
series F/FAST F/FAST - F/FAST
JESD-30 code R-GDIP-T16 R-PDIP-T16 - R-PDSO-G16
JESD-609 code e0 e0 - e0
length 19.3 mm 19.175 mm - 9.9 mm
Load capacitance (CL) 50 pF 50 pF - 50 pF
Logic integrated circuit type PARALLEL IN PARALLEL OUT PARALLEL IN PARALLEL OUT - PARALLEL IN PARALLEL OUT
Maximum Frequency@Nom-Su 90000000 Hz 90000000 Hz - 90000000 Hz
Number of digits 4 4 - 4
Number of functions 1 1 - 1
Number of terminals 16 16 - 16
Maximum operating temperature 70 °C 70 °C - 70 °C
Output polarity TRUE TRUE - TRUE
Package body material CERAMIC, GLASS-SEALED PLASTIC/EPOXY - PLASTIC/EPOXY
encapsulated code DIP DIP - SOP
Encapsulate equivalent code DIP16,.3 DIP16,.3 - SOP16,.25
Package shape RECTANGULAR RECTANGULAR - RECTANGULAR
Package form IN-LINE IN-LINE - SMALL OUTLINE
Peak Reflow Temperature (Celsius) NOT SPECIFIED NOT SPECIFIED - NOT SPECIFIED
power supply 5 V 5 V - 5 V
Maximum supply current (ICC) 38 mA 38 mA - 38 mA
propagation delay (tpd) 9 ns 9 ns - 9 ns
Certification status Not Qualified Not Qualified - Not Qualified
Maximum seat height 4.19 mm 4.44 mm - 1.75 mm
Maximum supply voltage (Vsup) 5.5 V 5.5 V - 5.5 V
Minimum supply voltage (Vsup) 4.5 V 4.5 V - 4.5 V
Nominal supply voltage (Vsup) 5 V 5 V - 5 V
surface mount NO NO - YES
technology TTL TTL - TTL
Temperature level COMMERCIAL COMMERCIAL - COMMERCIAL
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) - Tin/Lead (Sn/Pb)
Terminal form THROUGH-HOLE THROUGH-HOLE - GULL WING
Terminal pitch 2.54 mm 2.54 mm - 1.27 mm
Terminal location DUAL DUAL - DUAL
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED - NOT SPECIFIED
Trigger type POSITIVE EDGE POSITIVE EDGE - POSITIVE EDGE
width 7.62 mm 7.62 mm - 3.9 mm
minfmax 90 MHz 90 MHz - 90 MHz
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