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MC10H141FNR2

Description
Four−Bit Universal Shift Register
Categorylogic    logic   
File Size130KB,5 Pages
ManufacturerON Semiconductor
Websitehttp://www.onsemi.cn
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MC10H141FNR2 Overview

Four−Bit Universal Shift Register

MC10H141FNR2 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerON Semiconductor
Parts packaging codeQLCC
package instructionPLASTIC, LCC-20
Contacts20
Reach Compliance Code_compli
Is SamacsysN
Counting directionBIDIRECTIONAL
series10H
JESD-30 codeS-PQCC-J20
JESD-609 codee0
length8.965 mm
Logic integrated circuit typePARALLEL IN PARALLEL OUT
Maximum Frequency@Nom-Su250000000 Hz
Humidity sensitivity level1
Number of digits4
Number of functions1
Number of terminals20
Maximum operating temperature75 °C
Minimum operating temperature
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC20,.4SQ
Package shapeSQUARE
Package formCHIP CARRIER
Peak Reflow Temperature (Celsius)240
propagation delay (tpd)2 ns
Certification statusNot Qualified
Maximum seat height4.57 mm
surface mountYES
technologyECL
Temperature levelCOMMERCIAL EXTENDED
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
Trigger typePOSITIVE EDGE
width8.965 mm
minfmax250 MHz
Base Number Matches1
MC10H141
Four‐Bit Universal Shift
Register
Description
The MC10H141 is a four-bit universal shift register. This device is a
functional/pinout duplication of the standard MECL 10K™ part with
100% improvement in propagation delay and operation frequency and
no increase in power supply current.
Features
www.onsemi.com
Shift frequency, 250 MHz Min
Power Dissipation, 425 mW Typical
Improved Noise Margin 150 mV
16
1
PDIP−16
P SUFFIX
CASE 648−08
20 1
PLLC−20
FN SUFFIX
CASE 775−02
(Over Operating Voltage and Temperature Range)
Voltage Compensated
MECL 10K Compatible
These Devices are Pb-Free, Halogen Free and are RoHS Compliant
Table 1. TRUTH TABLE
SELECT
S1
S2
L
L
H
H
OPERATING
Q0
n + 1
Q1
n + 1
Q2
n + 1
Q3
n + 1
MODE
D0
Q1
n
DL
Q0
n
D1
Q2
n
Q0
n
Q1
n
D2
Q3
n
Q1
n
Q2
n
D3
DR
Q2
n
32
n
OUTPUTS
MARKING DIAGRAMS*
1 20
16
MC10H141P
AWLYYWWG
1
PDIP−16
A
WL, L
YY, Y
WW, W
G
10H141G
AWLYYWW
L Parallel Entry
H
L
H
Shift Right*
Shift Left*
Stop Shift
PLLC−20
* Outputs as exist after pulse appears at “C” input with
input conditions as shown (Pulse Positive transition of
clock input).
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
V
CC1
Q2
Q3
C
DR
D3
S2
V
EE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC2
Q1
Q0
DL
D0
D1
S1
D2
*For additional marking information, refer to
Application Note
AND8002/D.
ORDERING INFORMATION
Device
MC10H141FNR2G
MC10H141PG
Package
PLLC−20
(Pb-Free)
PDIP−16
(Pb-Free)
Shipping†
500 Tape & Reel
25 Units / Tube
Pin assignment is for Dual-in-Line Package.
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure,
BRD8011/D.
Figure 1. Pin Assignment
©
Semiconductor Components Industries, LLC, 2006
August, 2016
Rev. 9
1
Publication Order Number:
MC10H141/D

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