EEWORLDEEWORLDEEWORLD

Part Number

Search

MC10H105FNR2G

Description
Triple 2−3−2−Input OR/NOR Gate
Categorylogic    logic   
File Size122KB,5 Pages
ManufacturerON Semiconductor
Websitehttp://www.onsemi.cn
Environmental Compliance
Download Datasheet Parametric Compare View All

MC10H105FNR2G Overview

Triple 2−3−2−Input OR/NOR Gate

MC10H105FNR2G Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerON Semiconductor
Parts packaging codeQLCC
package instructionLEAD FREE, PLASTIC, LCC-20
Contacts20
Reach Compliance Codeunknow
Other featuresASYMMETRICAL INPUTS
series10H
JESD-30 codeS-PQCC-J20
JESD-609 codee3
length8.965 mm
Logic integrated circuit typeOR/NOR GATE
Number of functions3
Number of entries3
Number of terminals20
Maximum operating temperature75 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC20,.4SQ
Package shapeSQUARE
Package formCHIP CARRIER
method of packingTR
Peak Reflow Temperature (Celsius)260
power supply-5.2 V
Maximum supply current (ICC)23 mA
Prop。Delay @ Nom-Su1.3 ns
propagation delay (tpd)1.2 ns
Certification statusNot Qualified
Schmitt triggerNO
Maximum seat height4.57 mm
surface mountYES
technologyECL
Temperature levelCOMMERCIAL EXTENDED
Terminal surfaceTin (Sn)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperature40
width8.965 mm
MC10H105
Triple 2‐3‐2‐Input OR/NOR
Gate
Description
The MC10H105 is a triple 2-3-2-input OR/NOR gate. This
MECL 10H™ part is a functional/pinout duplication of the standard
MECL 10K™ family part, with 100% improvement in propagation
delay, and no increases in power-supply current.
Features
www.onsemi.com
Propagation Delay, 1.0 ns Typical
Power Dissipation 25 mW/Gate (same as MECL 10K)
Improved Noise Margin 150 mV
16
1
PDIP−16
P SUFFIX
CASE 648−08
20 1
PLLC−20
FN SUFFIX
CASE 775−02
(Over Operating Voltage and Temperature Range)
Voltage Compensated
MECL 10K Compatible
These Devices are Pb-Free, Halogen Free and are RoHS Compliant
4
5
9
10
11
13
12
V
CC1
= Pin 1
V
CC2
= Pin 16
V
EE
= Pin 8
3
2
6
7
14
15
MARKING DIAGRAMS*
1 20
16
MC10H105P
AWLYYWWG
1
PDIP−16
A
WL, L
YY, Y
WW, W
G
10H105G
AWLYYWW
PLLC−20
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
Figure 1. Logic Diagram
*For additional marking information, refer to
Application Note
AND8002/D.
V
CC1
A
out
A
out
A
in
A
in
B
out
B
out
V
EE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC2
C
out
C
out
C
in
C
in
B
in
B
in
B
in
ORDERING INFORMATION
Device
MC10H105FNG
MC10H105PG
Package
PLLC−20
(Pb-Free)
PDIP−16
(Pb-Free)
Shipping
46 Units / Tube
25 Units / Tube
Pin assignment is for Dual-in-Line Package.
Figure 2. Pin Assignment
©
Semiconductor Components Industries, LLC, 2006
August, 2016
Rev. 8
1
Publication Order Number:
MC10H105/D

MC10H105FNR2G Related Products

MC10H105FNR2G MC10H105_06 MC10H105MEL MC10H105
Description Triple 2−3−2−Input OR/NOR Gate Triple 2−3−2−Input OR/NOR Gate 10H SERIES, TRIPLE 3-INPUT OR/NOR GATE, PDSO16, EIAJ, SO-16 Triple 2−3−2−Input OR/NOR Gate

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1289  2233  1301  2603  1147  26  45  27  53  24 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号