MC100LVEL59
3.3V ECL Triple 2:1
Multiplexer
Description
The MC100LVEL59 is a 3.3 V triple 2:1 multiplexer with
differential outputs. The output data of the multiplexers can be
controlled individually via the select inputs or as a group via the
common select input. The flexible selection scheme makes the device
useful for both data path and random logic applications.
Features
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•
•
•
•
•
Individual or Common Select Controls
500 ps Typical Propagation Delays
ESD Protection: >2 kV HBM
The 100 Series Contains Temperature Compensation
SO−20 WB
DW SUFFIX
CASE 751D
PECL Mode Operating Range: V
CC
= 3.0 V to 3.8 V
with V
EE
= 0 V
•
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
=
−3.0
V to
−3.8
V
•
Internal Input Pulldown Resistors
MARKING DIAGRAM*
•
Q Output will Default LOW with Inputs Open or at V
EE
•
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
•
Moisture Sensitivity;
20
100LVEL59
AWLYYWWG
Pb Pkg
Level 1
Pb−Free Pkg
Level 3
For Additional Information, see Application Note AND8003/D
•
Flammability Rating: UL 94 V−O @ 0.125 in,
Oxygen Index 28 to 34
•
Transistor Count = 182 devices
1
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
•
Pb−Free Packages are Available*
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
November, 2006
−
Rev. 4
1
Publication Order Number:
MC100LVEL59/D
MC100LVEL59
V
CC
20
Q0
19
Q0
18
V
CC
17
Q1
16
Q1
15
V
CC
14
Q2
13
Q2
12
V
EE
11
1
0
1
0
1
0
1
2
3
D0b
4
5
6
D1b
7
8
9
10
COM_SEL D0a
SEL0 D1a
SEL1 D2a
D2b SEL2
Warning: All V
CC
and V
EE
pins must be externally connected
to Power Supply to guarantee proper operation.
Figure 1. Logic Diagram and Pinout: 20−Lead SOIC (Top View)
Table 1. PIN DESCRIPTION
Pins
D0a−D2a
D0b−D2b
SEL0−SEL2
COM_SEL
Q0−Q2; Q0−Q2
V
CC
V
EE
Function
ECL Input Data a
ECL Input Data b
ECL Individual Select Input
ECL Common Select Input
ECL Differential Outputs
Positive Supply
Negative Supply
Table 2. TRUTH TABLE
SEL
H
L
Data
a
b
Table 3. MAXIMUM RATINGS
Symbol
V
CC
V
EE
V
I
I
out
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
PECL Mode Power Supply
NECL Mode Power Supply
PECL Mode Input Voltage
NECL Mode Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction to Ambient)
Thermal Resistance (Junction to Case)
Wave Solder
0 lfpm
500 lfpm
Standard Board
<2 to 3 sec @ 248°C
20 SOIC
20 SOIC
20 SOIC
Condition 1
V
EE
= 0 V
V
CC
= 0 V
V
EE
= 0 V
V
CC
= 0 V
Continuous
Surge
V
I
V
CC
V
I
V
EE
Condition 2
Rating
8 to 0
−8
to 0
6 to 0
−6
to 0
50
100
−40
to +85
−65
to +150
140
100
30 to 35
265
Unit
V
V
V
V
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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2
MC100LVEL59
Table 4. LVPECL DC CHARACTERISTICS
V
CC
= 3.3 V; V
EE
= 0.0 V (Note 1)
−40°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
Characteristic
Power Supply Current
Output HIGH Voltage (Note 2)
Output LOW Voltage (Note 2)
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
0.5
2215
1470
2135
1490
Min
Typ
27
2295
1605
Max
32
2420
1745
2420
1825
150
0.5
2275
1490
2135
1490
Min
25°C
Typ
27
2345
1595
Max
32
2420
1680
2420
1825
150
0.5
2275
1490
2135
1490
Min
85°C
Typ
27
2345
1595
Max
32
2420
1680
2420
1825
150
Unit
mA
mV
mV
mV
mV
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary
±0.3
V.
2. Outputs are terminated through a 50
W
resistor to V
CC
−
2.0 V.
Table 5. LVNECL DC CHARACTERISTICS
V
CC
= 0.0 V; V
EE
=
−3.3
V (Note 3)
−40°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
Characteristic
Power Supply Current
Output HIGH Voltage (Note 4)
Output LOW Voltage (Note 4)
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
0.5
−1085
−1830
−1165
−1810
Min
Typ
27
−1005
−1695
Max
32
−880
−1555
−880
−1475
150
0.5
−1025
−1810
−1165
−1810
Min
25°C
Typ
27
−955
−1705
Max
32
−880
−1620
−880
−1475
150
0.5
−1025
−1810
−1165
−1810
Min
85°C
Typ
27
−955
−1705
Max
32
−880
−1620
−880
−1475
150
Unit
mA
mV
mV
mV
mV
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary
±0.3
V.
4. Outputs are terminated through a 50
W
resistor to V
CC
−
2.0 V.
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MC100LVEL59
Table 6. AC CHARACTERISTICS
V
CC
= 3.3 V; V
EE
= 0.0 V or V
CC
= 0.0 V; V
EE
=
−3.3
V (Note 5)
−40°C
Symbol
f
max
t
PLH
t
PHL
t
skew
t
JITTER
t
r
t
f
Characteristic
Maximum Toggle Frequency
Propagation
Delay
Output−Output Skew
Cycle−to−Cycle Jitter
Output Rise/Fall Times Q
(20%
−
80%)
200
DATA to Q/Q
SEL to Q/Q
COM_SEL to Q/Q
Any D
n
, D
m
to Q
TBD
540
200
340
340
340
Min
Typ
TBD
690
690
690
100
TBD
540
200
340
340
340
Max
Min
25°C
Typ
TBD
690
690
690
100
TBD
540
340
340
340
Max
Min
85°C
Typ
TBD
690
690
690
100
Max
Unit
GHz
ps
ps
ps
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. V
EE
can vary
±0.3
V.
Q
Driver
Device
Q
Z
o
= 50
W
D
Receiver
Device
Z
o
= 50
W
50
W
50
W
D
V
TT
V
TT
= V
CC
−
2.0 V
Figure 2. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D
−
Termination of ECL Logic Devices.)
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MC100LVEL59
ORDERING INFORMATION
Device
MC100LVEL59DW
MC100LVEL59DWG
MC100LVEL59DWR2
MC100LVEL59DWR2G
Package
SOIC−20
SOIC−20
(Pb−Free)
SOIC−20
SOIC−20
(Pb−Free)
Package
†
38 Units / Rail
38 Units / Rail
1000 / Tape & Reel
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
ECL Clock Distribution Techniques
−
Designing with PECL (ECL at +5.0 V)
−
ECLinPS I/O SPiCE Modeling Kit
−
Metastability and the ECLinPS Family
−
Interfacing Between LVDS and ECL
−
The ECL Translator Guide
−
Odd Number Counters Design
−
Marking and Date Codes
−
Termination of ECL Logic Devices
−
Interfacing with ECLinPS
−
AC Characteristics of ECL Devices
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