5-V Low-Drop Fixed Voltage Regulator
Version 2.0
TLE 4269
Features
q
q
q
q
q
q
q
q
q
q
Output voltage tolerance
≤ ±
2 %
Very low current consumption
Early warning
Reset output low down to
V
Q
= 1 V
Overtemperature protection
Reverse polarity proof
Settable reset threshold
Very low drop voltage
Wide temperature range
Integrated pull up resistor at logic outputs
Ordering Code Package
Q67000-A9190
Q67006-A9173
P-DIP-8-4
P-DSO-8-3 (SMD)
P-DSO-14-8 (SMD)
P-DSO-20-6 (SMD)
P-DIP-8-4
Type
TLE 4269 A
TLE 4269 G
P-DSO-8-3
w
TLE 4269 GM Q67006-A9288
TLE 4269 GL
w
New type
Functional Description
Q67006-A9192
This device is a voltage regulator with a fixed 5-V
output, e.g. in a P-DSO-8-1 package. The maximum
operating voltage is 45 V. The output is able to drive a
150 mA load. It is short circuit protected and the
thermal shutdown switches the output off if the junction
temperature is in excess of 150
°C.
A reset signal is
generated for an output voltage of
V
Q
< 4.6 V. The
reset threshold voltage can be decreased by external
connection of a voltage divider. The reset delay time
can be set by an external capacitor. Reset and sense
output have integrated pull up resistors. If the
integrated resistors are not desired
TLE 4279
can be
used. It is also possible to supervise the input voltage
by using an integrated comparator to give a low voltage
warning.
Semiconductor Group
1
P-DSO-14-8
P-DSO-20-1 /-6 /-7
1999-03-12
TLE 4269
Pin Configuration
(top view)
P-DIP-8-4
Ι
S
Ι
RE
D
P-DSO-8-3
1
2
3
4
8
7
6
5
AEP01668
Ι
S
Ι
RE
D
1
2
3
4
8
7
6
5
AEP01813
Q
SO
R
GND
Q
SO
R
GND
Pin Definitions and Functions (TLE 4269 A and TLE 4269 G)
Pin No.
1
2
3
4
5
6
7
8
Symbol
I
SI
RE
D
GND
R
SO
Q
Function
Input;
block directly to GND on the IC with a ceramic capacitor.
Sense Input;
if not needed connect to Q.
Reset Threshold;
if not needed connect to ground.
Reset Delay;
to select delay time, connect to GND via external
capacitor.
Ground
Reset Output;
the open-collector output is internally linked to Q
via a 20 kΩ pull-up resistor. Keep open, if not needed.
Sense Output;
the open-collector output is internally linked to the
output via a 20 kΩ pull-up resistor. Keep open, if not needed.
5-V Output;
connect to GND with a 10
µF
capacitor, ESR < 10
Ω.
Semiconductor Group
2
1999-03-12
TLE 4269
Pin Configuration
(top view)
P-DSO-14-8
1
2
3
4
5
6
7
14
13
12
11
10
9
8
AEP02248
RE
D
GND
GND
GND
GND
R
SI
Ι
GND
GND
GND
Q
SO
Pin Definitions and Functions (TLE 4269 GM)
Pin No.
1
2
3, 4, 5, 6
7
8
9
Symbol
RE
D
GND
R
SO
Q
Function
Reset Threshold;
if not needed connect to GND.
Reset Delay;
connect to GND via external delay capacitor for
setting delay time.
Ground
Reset Output;
open-collector output, internally connected to Q
via a pull-up resistor of 20 kΩ. Keep open, if not needed.
Sense Output;
open-collector output, internally connected to Q
via a 20 kΩ pull-up resistor. Keep open, if not needed.
5-V Output;
connect to GND with a 10
µF
capacitor, ESR < 10
Ω.
Ground
Input;
block to GND directly at the IC by a ceramic capacitor.
Sense Input;
if not needed connect to Q.
10, 11, 12 GND
13
14
I
SI
Semiconductor Group
3
1999-03-12
TLE 4269
Pin Configuration
(top view)
P-DSO-20-6
RE
D
N.C.
GND
GND
GND
GND
N.C.
N.C.
R
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
AEP01802
S
Ι
Ι
N.C.
GND
GND
GND
GND
N.C.
Q
SO
Pin Definitions and Functions (TLE 4269 GL)
Pin No.
1
2
4-7, 14-17
10
11
12
19
20
Symbol
RE
D
GND
R
SO
Q
I
SI
Function
Reset Threshold;
if not needed connect to GND.
Reset Delay;
to select delay time connect to GND via external
capacitor.
Ground
Reset Output;
the open-collector output is internally linked to
Q via 20 kΩ pull-up resistor. Keep open, if not needed.
Sense Output;
the open-collector output is internally linked to
Q via 20 kΩ pull-up resistor. Keep open, if not needed.
Output;
connect to GND with a 10
µF
capacitor, ESR < 10
Ω.
Input;
block directly to GND at the IC by a ceramic capacitor.
Sense Input;
if not needed connect to Q.
Semiconductor Group
4
1999-03-12
TLE 4269
Circuit Description
The control amplifier compares a reference voltage, made highly accurate by resistance
balancing, with a voltage proportional to the output voltage and drives the base of the
series PNP transistor via a buffer. Saturation control as a function of the load current
prevents any over-saturation of the power element.
In the reset generator block a comparator compares a reference voltage independent of
the input voltage with the scaled-down output voltage. If the output voltage reaches 4.6 V
the reset delay capacitor is discharged and the reset output is set to low. This low is
guaranteed down to an output voltage of 1 V. As the output voltage increases again,
from 4.6 V onward the reset delay capacitor is charged with constant current. When the
capacitor voltage reaches the upper switching threshold
V
dT
, the reset returns to high.
By choosing the value of this capacitor, the reset delay time can be selected over a wide
range. With the reset threshold input RE it is possible to lower the reset threshold
V
rt
. If
pin RE is connected to pin Q via a voltage divider, for example, the reset condition is
reached when this voltage is decreased below the switching threshold
V
re
of 1.35 V.
Another comparator compares the signal of the pin SI, normally fed by a voltage divider
from the input voltage, with the reference and gives an early warning on the pin SO. It is
also possible to superwise an other voltage e.g. of a second regulator, or to build a
watchdog circuit with few external components.
Application Description
The input capacitor
C
I
is necessary for compensating line influences. Using a resistor of
approx. 1
Ω
in series with
C
I
, the oscillating circuit consisting of input inductivity and input
capacitance can be damped. The output capacitor
C
Q
is necessary for the stability of the
regulating circuit. Stability is guaranteed at values
≥
10
µF
and an ESR
≤
10
Ω
within the
operating temperature range. For small tolerances of the reset delay the spread of the
capacitance of the delay capacitor and its temperature coefficient should be noted.
Semiconductor Group
5
1999-03-12
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