SL23EP04
Not Recommended for New Designs
Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer (ZDB)
Key Features
10 to 220 MHz operating frequency range
Low output clock skew: 60ps-typ
Low output clock Jitter:
Description
The SL23EP04 is a low skew, low jitter and low power
Zero Delay Buffer (ZDB) designed to produce up to four
(4) clock outputs from one (1) reference input clock, for
high speed clock distribution applications.
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Low part-to-part output skew: 150 ps-typ
3.3V to 2.5V power supply range
Low power dissipation:
-
12 mA-typ at 66MHz and VDD=3.3V
- 10 mA-typ at 66MHz and VDD=2.5V
One input drives 4 outputs
The product has an on-chip PLL and a feedback pin
(FBK) which can be used to obtain feedback from any
one of the 4 output clocks. The SL23EP04 offers X/2,1X
and 2X frequency options at the output with respect to
input reference clock. Refer to the “Product Configuration
Table” for the details of these options.
The SL23EP04-1H and -2H High Drive version operates
up to 220 MHz and 200MHz at 3.3 and 2.5V power
supplies respectively. The standard versions -1 and -2
operate up to 167MHz and 135MHz at 3.3V and 2.5V
power supplies respectively with CL=15pF output load.
The SL23EP04 enter into Power Down (PD) mode if the
input at CLKIN is DC (GND to VDD). In this state all 4
output clocks are tri-stated and the PLL is turned off,
leading to 8μA-typ power supply current draw.
Multiple configurations and drive options
Available in 8-pin SOIC package
SpreadThru™ PLL that allows use of SSCG
Available in Commercial and Industrial grades
Printers, MFPs and Digital Copiers
PCs and Work Stations
Routers, Switchers and Servers
Datacom and Telecom
High-Speed Digital Embeded Systems
Applications
Benefits
Up to four (4) distribution of input clock
Standard and High-Drive levels to control
impedance level, frequency range and EMI
Low skew, jitter and power dissipation
Block Diagram
FBK
CLKIN
Low Power and
Low Jitter
PLL
CLKA1
CLKA2
(Divider for -2 only)
/2
CLKB1
CLKB2
VDD
GND
Rev 2.1, May 15, 2008
Page 1 of 15
2400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
www.silabs.com
SL23EP04
Pin Configuration
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CLKA1
CLKA2
GND
2
3
4
7
CLKIN
1
8
FBK
VDD
6
CLKB2
CLKB1
5
8-Pin SOIC
Pin Description
Pin
Number
1
2
3
4
5
6
7
8
Pin Name
Pin Type
Input
Pin Description
CLKIN
Reference Frequency Clock Input. Weak pull-down (250kΩ).
Buffered Clock Output Weak pull-down (250kΩ).
Power Ground.
CLKA1
CLKA2
GND
CLKB1
CLKB2
VDD
FBK
Output
Output
Power
Output
Output
Power
Input
Buffered Clock Output. Weak pull-down (250kΩ).
Buffered Clock Output. Weak pull-down (250kΩ).
Buffered Clock Output. Weak pull-down (250kΩ).
2.5V to 3.3V Power Supply.
PLL Feedback Input. This pin must be connected to one of the clock outputs.
May 15, 2008
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SL23EP04
General Description
High and Low-Drive Product Options
The SL23EP04 is a low skew, low jitter Zero Delay Buffer All SL23EP04 products are offered with the high drive
with very low operating current.
“-1H” and “-2H” as well as the standard drive “-1” and “-2”
options. These drive options enable the user to control
The product includes an on-chip high performance PLL
load levels, frequency range and EMI levels. Refer to the
that locks into the input reference clock and produces
electrical tables for the details of the drive levels.
four (4) output clock drivers tracking the input reference
clock for systems requiring clock distribution.
Skew and Zero Delay
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in addition to FBK pin used for internal PLL feedback,
All outputs should drive the similar load to achieve output-
there are two (2) banks with two (2) outputs in each bank,
to-output skew and input-to-output delay specifications as
bringing the number of total available output clocks to
given in the switching electrical tables. However, the delay
four (4).
between input and outputs can be adjusted by changing
the load at FBK pin relative to the banks A and B clocks
Input and output Frequency Range
since FBK pin is the feedback to the internal PLL.
The input and output frequency is the same (1x) for
SL23EP04-1 and -1H versions. For SL23EP04-2 and -
In addition, the input reference clock rise and fall time
2H versions, the output frequency is 1/2x, 1x or 2x of
should be similar to the output rise and fall time to obtain
the CLKIN as given in the “Available SL23EP04
the best skew results.
Configurations” Table 1. But, the frequency range
depends on VDD, drive levels and CL (Load
Power Supply Range (VDD)
Capacitance) as given in the electrical specifications
tables.
The SL23EP04 is designed to operate from 3.3V (3.63V-
max) to 2.5V (2.25V-min) VDD power supply range. An
When the input clock frequency is DC (from GND to
internal on-chip voltage regulator is used to provide to
VDD), this input state is detected by an input level
detection circuitry and all four (4) clock outputs are forced PLL constant power supply of 1.8V internally. This leads
to a consistent and stable PLL electrical performance in
to Hi-Z. The PLL is shutdown to save power. In this
terms of skew, jitter and power dissipation. The
shutdown state, the product draws less than 12 μA
SL23EP04 I/O is powered by using VDD.
(8 μA –typ) supply current.
SpreadThru™ Feature
If a Spread Spectrum Clock (SSC) were to be used as
an input clock, the SL23EP04 is designed to pass the
modulated Spread Spectrum Clock (SSC) signal from
its reference CLKIN input to the output clocks. The
same spread spectrum characteristics at the input are
passed through the PLL and drivers without any
degradation in spread percent (%), spread profile and
modulation frequency.
Contact SLI for 1.8V power supply ZDB called
SL23EPL04.
Device
Feedback From
Bank-A or Bank-B
Bank-A
Bank-B
Bank-A Frequency
Reference
Reference
Bank-B Frequency
Reference
Reference
Reference / 2
SL23EP04-1 and 1H
SL23EP04-2 and -2H
SL23EP04-2 and -2H
2 x Reference
Table 1. Available SL23EP04 Configurations
May 15, 2008
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SL23EP04
Absolute Maximum Ratings (All Products)
Description
Supply voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Ambient Operating Temperature
Storage Temperature
Junction Temperature
In operation, C-Grade
In operation, I-Grade
No power is applied
Condition
Min
-0.5
-0.5
0
-40
-65
-
-
Max
4.6
VDD+0.5
70
85
Unit
V
V
°C
°C
°C
°C
°C
V
V
V
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150
125
260
In operation, power is applied
JEDECCC22-A114D
JEDECCC22-A115D
Soldering Temperature
ESD Rating (Human Body Model)
ESD Rating (Machine Model)
-4000
-1500
-200
4000
1500
200
ESD Rating (Change Device Model)
JEDECCC22-C101C
Operating Conditions (C-Grade and VDD=3.3V)
Description
Symbol
VDD
TA
VIH
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C
Condition
Min
0
-
-
-
Typ
3.3
-
5
Max
3.63
70
7
-
-
Unit
V
°C
Operating Voltage
VDD+/-10%
2.97
Operating Temperature
Input Capacitance
Output Impedance
Output Impedance
Ambient Temperature
Pins 1 and 8
pF
Ω
Ω
R
OUT-1
R
OUT-2
High Drive (-1H and -2H)
28
40
Standard Drive (-1 and -2)
DC Electrical Characteristics (C-Grade and VDD=3.3V)
Description
Symbol
VINL
IINL
VINH
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C
Condition
Min
–
2.0
–
–
–
–
Typ
–
–
Max
0.8
50
50
Unit
V
V
Input LOW Voltage
Input LOW Current
Pins 1 and 8
Pins 1 and 8
Input HIGH Voltage
VDD+0.3
0 < VIN < 0.8V, Pins 1 and 8
2.4V < VIN < VDD
Pins 1 and 8
20
20
–
–
µA
µA
V
V
Input HIGH Current
IINH
VOL
Output LOW Voltage
IOL = 8 mA ( -1, -2 drives)
0.4
0.4
IOL = 12 mA (-1H, -2H drives)
May 15, 2008
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SL23EP04
DC Electrical Characteristics (C-Grade and VDD=3.3V – Cont.)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C
Description
Output HIGH Voltage
Power Down Supply
Current
Symbol
VOH
Condition
IOH = –8 mA (-1, -2 drives)
IOH = –12 mA (-1H, -2H drives)
Min
2.4
2.4
–
–
–
–
–
Typ
–
–
8
Max
–
–
Unit
V
V
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IDDPD
IDD1
IDD2
IDD3
IDD4
RPD
Measured when CLKIN= GND to VDD
or floating
All Outputs CL=0, 33.3 MHz CLKIN
All versions
All Outputs CL=0, 66.6 MHz CLKIN
All versions
12
14
17
20
23
Power Supply Current
10
12
14
16
Power Supply Current
Power Supply Current
Power Supply Current
Pull-down Resistors
All Outputs CL=0, 133.3 MHz CLKIN
All versions
All Outputs CL=0, 166.6 MHz CLKIN
All versions
Pin-1, 2, 3, 5, and 6
150
250
350
µA
mA
mA
mA
mA
kΩ
Switching Electrical Characteristics (C-Grade and VDD=3.3V)
Description
Symbol
FOUT1
FOUT2
FOUT3
FOUT4
FOUT5
FOUT6
DC1
DC2
DC3
DC4
DC5
tr/f1
tr/f2
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C
Condition
Min
10
10
10
10
10
10
30
40
45
45
45
-
-
Typ
-
-
-
-
-
-
Max
220
180
135
180
135
100
70
60
55
55
55
Unit
MHz
MHz
MHz
MHz
MHz
MHz
%
%
%
%
%
CL=15pf, -1H and -2H versions
CL=22pf, -1H and -2H versions
CL=30pf, -1H and -2H versions
CL=15pf, -1, and -2 versions
CL=22pf, -1 and -2 versions
CL=30pf, -1 and -2 versions
Output Frequency Range
Input Duty Cycle
Measured at VDD/2, all versions
50
50
50
50
50
-
-
Output Duty Cycle
Output Duty Cycle
Output Duty Cycle
Output Duty Cycle
CL=30pF, Fout=66 MHz, all versions
Measured at 1.4V
CL=15pF, Fout=66 MHz, all versions
Measured at VDD/2
CL=15pF, Fout=133 MHz, all versions
Measured at VDD/2
CL=15pF, Fout=166 MHz, all versions
Measured at VDD/2
CL=30pF, -1 and -2 versions,
measured from 0.8V to 2.0V
CL=15pF, -1 and -2 versions,
measured from 0.8V to 2.0V
Output Rise/Fall Time
Output Rise/Fall Time
2.2
1.5
ns
ns
May 15, 2008
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