Ordering number : EN*5919
CMOS IC
LC74775, 74775M
On-Screen Display Controller IC
Preliminary
Overview
The LC74775/M is an on-screen display controller CMOS
IC that displays characters and patterns on the TV screen
under microprocessor control. This IC includes a built-in
PDC/VPS/UDT interface circuit.
Package Dimensions
unit: mm
3196-DIP30SD
[LC74775]
Functions
• Display format: 24 characters by 12 rows (Up to 288
characters)
• Character format: 12 (horizontal)
×
18 (vertical) dots
• Character sizes: Three sizes each in the horizontal and
vertical directions
• Characters in font: 128 (Of the 128 characters, one is a
space character (7E hexadecimal)
and one is a transparent space
character (7F hexadecimal))
• Initial display positions: 64 horizontal positions and 64
vertical positions
• Blinking: Specifiable in character units
• Blinking types: Two periods supported:
1.0 second and 0.5 second
• Blanking: Over the whole font (12
×
18 dots)
• Background color: 8 colors (internal synchronization
mode): 4f
SC
and 2f
SC
Blue background only: NTSC
• Line background color: Three lines can be set up.
8 line background colors (in
internal synchronization mode):
4f
SC
and 2f
SC
• External control input: 8-bit serial input format
• On-chip sync separator circuit
• Video outputs: PAL and NTSC format composite video
outputs
• On-chip PDC/VPS/UDT interface circuit supporting I
2
C
• Package: DIP30SD
MFP30S
SANYO: DIP30SD
unit: mm
3216A-MFP30S
[LC74775M]
SANYO: MFP30S
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
N1198RM(OT) No. 5919-1/35
LC74775, 74775M
Pin Assignment
No. 5919-2/35
LC74775, 74775M
Pin Functions
Pin no.
1
2
Pin
V
SS
1
Xtal
IN
Xtal
OUT
(MUTE)
Crystal oscillator input
switching
(CHABLK)
I
2
C clock input
LC oscillator
connections
Crystal oscillator
(MUTE input)
Ground
Function
Ground connection (digital system ground)
These pins are used either to connect the crystal and capacitors used to form an external
crystal oscillator circuit to generate the internal synchronizing signals, or to input an external
clock signal (2fsc or 4fsc). As a mask option, the Xtal
OUT
pin can be set to function as
the MUTE input pin. When this pin is set low, the video output is held at the pedestal level.
(A pull-up resistor is built in and the input has hysteresis characteristics.)
Switches the mode between external clock input and crystal oscillator operation. A low level
selects crystal oscillator operation and a high level selects external clock input. As a mask
option, the CTRL1 input pin can be set to function as the CHABLK (character
.
frame)
output. This is a 3-value output.
Clock input for the PDC/VPS data output. I
2
C bus.
Connection for the external coil and capacitor for the oscillator used to generate
the character output dot clock
Outputs the state of the external synchronizing signal presence/absence judgment. Outputs
a high level when synchronizing signals are present.
Outputs either the crystal oscillator clock if CS and RST are low, or the VCO clock if CS
and RST are high.
(This signal is not output after a command reset.)
Enable input for the OSD serial data input.
Serial data input is enabled when this pin is low.
A pull-up resistor is built in and the input has hysteresis characteristics.
Serial data input enable pin.
A pull-up resistor is built in and the input has hysteresis characteristics.
Serial data input.
A pull-up resistor is built in and the input has hysteresis characteristics.
Composite video signal level adjustment power supply (analog system power supply)
Charge pump output. Connect a low-pass filter to this pin.
VCO oscillator control voltage input. (For data slicing)
Ground (VCO ground)
VCO oscillator range adjustment resistor connection
This pin must either be connected to ground or left open
Power supply (+5 V)
Video signal output
Ground
Video signal input
Video signal input
Power supply (+5 V)
Sync separator circuit input
Slice level output
Composite synchronizing
signal output
I
2
C
bus data I/O
Power supply (+5 V: VCO power supply)
Composite video signal output
Ground (analog system ground)
Composite video signal input
SECAM chrominance signal input
Power supply (+5 V: digital system power supply)
Video signal input to the internal sync separator circuit
Slice level verification pin
Internal sync separator circuit composite synchronizing signal output. The signal actually
output can be switched by MOD0 and SEL0. The DAV signal is output in the initial state.
PDC/VPS data I/O.
The I
2
C bus write address is [0111 1100].
The I
2
C bus read address is [0111 1101].
Background color phase adjustment resistor connection
System reset input.
A pull-up resistor is built in and the input has hysteresis characteristics.
Power supply (+5 V: digital system power supply)
Notes
3
4
CTRL1
(CHABLK)
SCL
OSC
IN
OSC
OUT
5
6
7
8
SYNC
JDC
External synchronizing
signal judgment output
9
CS
Enable input
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
SCLK
SIN
V
DD
2
CP
OUT
VCO
IN
V
SS
3
VCO
R
NC
V
DD
3
CV
OUT
V
SS
2
CV
IN
CV
CR
V
DD
1
SYN
IN
SEPC
SEP
OUT
SDA
Clock input
Data input
Power supply
Charge pump output
Oscillator control voltage input
Ground
Oscillator range adjustment
27
28
29
30
CDLR
RST
V
DD
1
Background color phase
adjustment
Reset input
Power supply (+5 V)
Note:
*Both
V
DD
1 pins must be connected to power.
No. 5919-3/35
LC74775, 74775M
Absolute Maximum Ratings
Paremeter
Maximum supply voltage
Maximum input voltage
Maximum output voltage
Allowable power dissipation
Operating temperature
Storage temperature
Symbol
V
DD
max
V
IN
max
V
OUT
max
Pd max
Topr
Tstg
Conditions
V
DD
1, V
DD
2, and V
DD
3
All input pins
SDA, SYNC
JDG
, and SEP
OUT
Ta = 25°C
Ratings
V
SS
– 0.3 to V
SS
+ 6.5
V
SS
– 0.3 to V
DD
1 + 0.3
V
SS
– 0.3 to V
DD
1 + 0.3
350
–30 to + 70
–40 to + 125
Unit
V
V
V
mW
°C
°C
Allowable Operating Ranges
Ratings
Paremeter
Supply voltage
Symbol
V
DD
1
V
DD
2
V
IH
1
Input high-level voltage
V
IH
2
V
IH
3
Input low-level voltage
V
IL
1
V
IL
2
Pull-up resistance
Composite video signal
input voltage
Input voltage
R
PU
V
IN
1
V
IN
2
V
IN
3
f
OSC
1
Oscillator frequencies
f
OSC
2
f
OSC
3
V
DD
1, V
DD
3
V
DD
2
CS, SIN, SCLK, SDA, SCL,
RST, MUTE
CTRL1
RST, CS, SIN, SCLK, SDA, SCL,
MUTE
CTRL1
RST, CS, SIN, SCLK, MUTE
Applies to pins set up by options.
CV
IN
, CV
CR
: V
DD
1 = 5V
SYN
IN
: V
DD
1 = 5V
Xtal
IN
(when used for external clock input)
f
IN
= 2fsc or 4fsc: V
DD
1= 5V
Xtal
IN
and Xtal
OUT
oscillator pins (2fsc: PAL)
Xtal
IN
and Xtal
OUT
oscillator pins (4fsc: PAL)
OSC
IN
and OSC
OUT
oscillator pins (LC oscillator)
5
1.5
0.10
8.867
17.734
10
Conditions
min
4.5
4.5
0.8V
DD
1
0.8V
DD
1
0.7V
DD
1
V
SS
– 0.3
V
SS
– 0.3
25
50
2.0
2.0
2.5
5.0
typ
5.0
5.0
max
5.5
6.5
5.5
V
DD
1 + 0.3
V
DD
1 + 0.3
0.2V
DD
1
0.3V
DD
1
90
Unit
V
V
V
V
V
V
V
kΩ
Vp-p
Vp-p
Vp-p
MHz
MHz
MHz
Note: Applications must be especially cautious about noise when using the Xtal
IN
input pin in clock input mode.
Electrical Characteristics
at Ta = –30 to +70°C, V
DD
1 = 5 V unless otherwise specified
Ratings
Paremeter
Input off leakage current
Output off leakage current
Output high-level voltage
Symbol
I
leak
1
I
leak
2
V
OH
1
V
OL
1
V
OL
2
Three-value output voltage
V
O
CV
IN
, CV
CR
CV
OUT
, SDA
SEP
OUT
, CP
OUT
, SYNC
JDG
V
DD
1 = 4.5V, I
OH
= –1.0 mA
SEP
OUT
, CP
OUT
, SYNC
JDG
V
DD
1 = 4.5 V, I
OL
= 1.0 mA
SDA: V
DD
1 = 5.0V, I
OL
= 3.0 mA
H
CHABLK: V
DD
1 = 5.0 V
M
L
I
IH
Input current
I
IL
I
DD
1
I
DD
2
SYNC level
V
SN
CTRL1, SDA, SCL, VCOIN
V
IN
= V
SS
1
V
DD
1 and V
DD
3: With all outputs open
Xtal: 17.734 MHz, LC: 8 MHz
V
DD
2: V
DD
2 = 5 V
(1)
CV
OUT
: V
DD
1 = 5.0 V,
V
DD
2 = 5.0 V
(2)
(3)
(1)
Pedestal level
V
PD
CV
OUT
: V
DD
1 = 5.0 V,
V
DD
2 = 5.0 V
(2)
(3)
0.80
1.00
1.40
1.37
1.57
1.97
–1
µA
RST, CS, SIN, SCLK, SDA, SCL, CTRL1,
MUTE, VCOIN: V
IN
= V
DD
1
3.3
1.8
0
3.5
Conditions
min
typ
max
1
1
Unit
µA
µA
V
Output low-level voltage
1.0
0.4
5.0
2.3
0.8
1
V
V
V
V
V
µA
Operating mode current drain
40
20
mA
mA
V
V
V
V
V
V
Continued on next page.
No. 5919-4/35
LC74775, 74775M
Continued from preceding page.
Paremeter
Symbol
Conditions
(1)
Color burst low level
V
CBL
CV
OUT
: V
DD
1 = 5.0V,
V
DD
2 = 5.0V
(2)
(3)
(1)
Color burst high level
V
CBH
CV
OUT
: V
DD
1 = 5.0V,
V
DD
2 = 5.0V
(2)
(3)
(1)
Background color
(other than blue) low level
V
RSL
0
CV
OUT
: V
DD
1 = 5.0V,
V
DD
2 = 5.0V
(2)
(3)
(1)
Background color
(other than blue) high level
V
RSH
0
CV
OUT
: V
DD
1 = 5.0V,
V
DD
2 = 5.0V
(2)
(3)
(1)
Blue background color 1
low level
V
RSL
1
CV
OUT
: V
DD
1 = 5.0V,
V
DD
2 = 5.0V
(2)
(3)
(1)
Blue background color 2
low level
V
RSL
2
CV
OUT
: V
DD
1 = 5.0V,
V
DD
2 = 5.0V
(2)
(3)
(1)
Blue background color 1
and 2 high level
V
RSH
CV
OUT
: V
DD
1 = 5.0V,
V
DD
2 = 5.0V
(2)
(3)
(1)
Frame level 0
V
BK
0
CV
OUT
: V
DD
1 = 5.0V,
V
DD
2 = 5.0V
(2)
(3)
(1)
Frame level 1
V
BK
1
CV
OUT
: V
DD
1 = 5.0V,
V
DD
2 = 5.0V
(2)
(3)
(1)
Character level
V
CHA
CV
OUT
: V
DD
1 = 5.0V,
V
DD
2 = 5.0V
(2)
(3)
Notes: (1): When the sync level = 0.8 V
(2): When the sync level = 1.0 V
(3): When the sync level = 1.4 V
The blue background color (1 or 2) is set as an option.
Ratings
min
typ
1.07
1.27
1.67
1.67
1.87
2.27
1.23
1.43
1.83
2.37
2.57
2.97
1.16
1.36
1.76
1.52
1.72
2.12
2.01
2.21
2.61
1.50
1.70
2.10
2.08
2.28
2.68
2.65
2.85
3.25
max
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
No. 5919-5/35
51mcu
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