PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD4564441-A75, 4564841-A75
64M-bit Synchronous DRAM, 133MHz
4-bank, LVTTL
Description
The
µ
PD4564441-A75, 4564841-A75 are high-speed 67,108,864-bit synchronous dynamic random-access
memories, organized as 4,194,304
×
4
×
4 and 2,097,152
×
8
×
4 (word
×
bit
×
bank), respectively.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).
These products are packaged in 54-pin plastic TSOP (II).
Features
•
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
•
Pulsed interface
•
Possible to assert random column address in every cycle
•
Quad internal banks controlled by A12 and A13 (Bank Select)
•
Programmable Wrap sequence (Sequential / Interleave)
•
Programmable burst length (1, 2, 4, 8 and full page)
•
/CAS latency (3)
•
Automatic precharge and controlled precharge
•
CBR (auto) refresh and self refresh
• ×4, ×8
organization
•
Single 3.3 V
±
0.3 V power supply
•
LVTTL compatible inputs and outputs
•
4,096 refresh cycles / 64 ms
•
Burst termination by Burst stop command and Precharge command
Ordering Information
Part number
Organization
(word
×
bit
×
bank)
4M
×
4
×
4
2M
×
8
×
4
Clock frequency
MHz (MAX.)
133
Package
54-pin Plastic TSOP (II)
(400 mil)
µ
PD4564441G5-A75-9JF
µ
PD4564841G5-A75-9JF
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M13977EJ3V0DS00 (3rd edition)
Date Published April 1999 NS CP (K)
Printed in Japan
The mark
•
shows major revised points.
©
1998
µ
PD4564441-A75, 4564841-A75
Pin Configurations
/xxx indicates active low signal.
[
µ
PD4564441-A75 ]
54-pin Plastic TSOP (II) (400 mil)
4M words
×
4 bits
×
4 banks
V
CC
NC
V
CC
Q
NC
DQ0
V
SS
Q
NC
NC
V
CC
Q
NC
DQ1
V
SS
Q
NC
V
CC
NC
/WE
/CAS
/RAS
/CS
A13
A12
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
Vss
NC
VssQ
NC
DQ3
VccQ
NC
NC
VssQ
NC
DQ2
VccQ
NC
Vss
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
A0 to A13
CLK
CKE
/CS
/RAS
/CAS
/WE
DQM
V
CC
V
SS
V
CC
Q
V
SS
Q
NC
Note
: Address inputs
: Clock input
: Clock enable
: Chip select
: Row address strobe
: Column address strobe
: Write enable
: DQ mask enable
: Supply voltage
: Ground
: Supply voltage for DQ
: Ground for DQ
: No connection
Note
A0 to A11 : Row address inputs
A0 to A9 : Column address inputs
A12, A13 : Bank select
DQ0 to DQ3 : Data inputs / outputs
Preliminary Data Sheet M13977EJ3V0DS00
3
µ
PD4564441-A75, 4564841-A75
[
µ
PD4564841-A75 ]
54-pin Plastic TSOP (II) (400 mil)
2M words
×
8 bits
×
4 banks
V
CC
DQ0
V
CC
Q
NC
DQ1
V
SS
Q
NC
DQ2
V
CC
Q
NC
DQ3
V
SS
Q
NC
V
CC
NC
/WE
/CAS
/RAS
/CS
A13
A12
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
Vss
DQ7
VssQ
NC
DQ6
VccQ
NC
DQ5
VssQ
NC
DQ4
VccQ
NC
Vss
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
A0 to A13
CLK
CKE
/CS
/RAS
/CAS
/WE
DQM
V
CC
V
SS
V
CC
Q
V
SS
Q
NC
Note
: Address inputs
: Clock input
: Clock enable
: Chip select
: Row address strobe
: Column address strobe
: Write enable
: DQ mask enable
: Supply voltage
: Ground
: Supply voltage for DQ
: Ground for DQ
: No connection
Note
A0 to A11 : Row address inputs
A0 to A8 : Column address inputs
A12, A13 : Bank select
DQ0 to DQ7 : Data inputs / outputs
4
Preliminary Data Sheet M13977EJ3V0DS00
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