®
EMIF10-COM01C1
EMI FILTER
INCLUDING ESD PROTECTION
IPAD™
MAIN PRODUCT CHARACTERISTICS
EMI filtering and ESD protection for:
■
■
■
Computers and printers
Communication systems
Mobile phones
DESCRIPTION
The EMIF10-COM01C1 is a highly integrated
device designed to suppress EMI / RFI noise in all
systems subjected to electromagnetic interfer-
ences. The EMIF10 Flip-Chip packaging means
the package size is equal to the die size.
Additionally, this filter includes an ESD protection
circuitry which prevents the protected device from
destruction when subjected to ESD surges up to
15 kV.
BENEFITS
■
EMI symmetrical (I/O) low-pass filter
■
Coating resin on back side
2
■
Very low PCB space consuming: < 7mm
■
Very thin package: 0.65 mm
■
High efficiency in ESD suppression on both
input & output pins
■
High reliability offered by monolithic integration
Coated Flip-Chip
(25 Bumps)
Table 1: Order Code
Part Number
EMIF010-COM01C1
Figure 1: Pin Configuration (Ball side)
COMPLIES WITH THE FOLLOWING STANDARDS:
IEC61000-4-2 level 4
15kV (air discharge)
8kV (contact discharge)
O
so
b
te
le
r
P
uc
od
s)
t(
bs
-O
et
l
o
E
I5
I10
GND
010
P
e
D
I4
od
r
B
I2
s)
t(
uc
Marking
FE
A
I1
C
I3
1
2
3
4
5
I9
I8
I7
I6
GND
GND
GND
GND
09
08
07
06
05
04
03
02
01
Figure 2: Basic cell configuration
Low-pass Filter
Input
Output
R
I/O
= 200
Ω
C
line
= 45 pF
TM:
IPAD is a trademark of STMicroelectronics.
March 2005
REV. 1
1/7
EMIF10-COM01C1
Table 2: Absolute Ratings
(T
amb
= 25°C)
Symbol
V
PP
T
j
T
op
T
stg
Parameter and test conditions
ESD discharge IEC61000-4-2, air discharge
ESD discharge IEC61000-4-2, contact discharge
Junction temperature
Operating temperature range
Storage temperature range
Value
15
8
125
- 40 to + 85
- 55 to + 150
Unit
kV
°C
°C
°C
Table 3: Electrical Characteristics
(T
amb
= 25°C)
Symbol
V
BR
I
RM
V
RM
V
CL
R
d
I
PP
R
I/O
C
line
Symbol
V
BR
I
RM
R
d
R
I/O
C
line
t
LH
At 0V bias
I
R
= 1 mA
V
RM
= 3V per line
I
PP
= 10A, t
p
= 2.5µs
Parameter
Breakdown voltage
Leakage current @ V
RM
Stand-off voltage
Clamping voltage
Dynamic impedance
Peak pulse current
Series resistance between Input &
Output
Input capacitance per line
slope : 1 / R
d
V
CL
V
BR
V
RM
I
RM
I
R
I
Test conditions
Vinput = 2.8V
O
so
b
te
le
r
P
uc
od
s)
t(
bs
-O
et
l
o
P
e
od
r
I
PP
s)
t(
uc
Max.
10
500
Unit
V
nA
Ω
220
50
25
Ω
pF
ns
V
Min.
6
Typ.
8
1
180
200
45
Rload = 100kΩ
2/7
EMIF10-COM01C1
Figure 3: S21(db) attenuation measurement
EMIF10-COM01C1: Typical S21(dB) measurement on line I10/O10
0.00
dB
-5.00
-10.00
-15.00
-20.00
-25.00
-30.00
-35.00
-40.00
-45.00
-50.00
1.0M
3.0M
10.0M
30.0M
100.0M 300.0M
f/Hz
1.0G
3.0G
Figure 4: Analog crosstalk
EMIF10-COM01C1: Typical A1/A2 crosstalk measurement
0.00
dB
-5.00
-10.00
-15.00
-20.00
-25.00
-30.00
-35.00
-40.00
-45.00
-50.00
-55.00
-60.00
-65.00
-70.00
-75.00
-80.00
1.0M
3.0M
10.0M
30.0M
100.0M
f/Hz
300.0M
1.0G
3.0G
Note:
Spikes at high frequencies are induced by the PCB layout
Figure 5: ESD response to IEC61000-4-2
(+15kV air discharge) on one input V(in) and on
one output (Vout)
Figure 6: ESD response to IEC61000-4-2 (-15kV
air discharge) on one input V(in) and on one
output (Vout)
V(in1)
V(out1)
Figure 7: Rise time measurement
b
O
so
te
le
r
P
uc
od
In
s)
t(
bs
-O
et
l
o
P
e
od
r
s)
t(
uc
V(in1)
V(out1)
EMIF10-COM01C1
Out
Vout
Square signal
Generator Vc = 2.8V
Vin
100k
Vout
Vin
3/7
EMIF10-COM01C1
Figure 8: Capacitance versus reverse applied
voltage
C(pF)
50
F=1MHz
Vosc=30mV
40
30
20
10
0
1
2
VR(V)
3
4
5
Figure 9: Aplac model
200R
in
MODEL = demif10
out
MODEL = demif10
sub
PCB grounding recommendations
In order to ensure a good efficiency in terms of ESD protection and filtering behavior, we recommend to
implement microvias (100 µm dia.) between the GND bumps and the GND layer. GND bumps can be con-
nected together in PCB layer 1, and in addition, if possible, use through hole vias (200 µm dia.) in both
O
sides of filter to improve contact to GND (layer). This layout will minimize the distance to the ground and
thus parasitic inductances. In addition, we recommend to have GND plane wherever possible.
so
b
te
le
r
P
uc
od
s)
t(
bs
-O
et
l
o
P
e
od
r
s)
t(
uc
Demif10 model
BV = 7
IBV = 1m
CJO = 25p
M = 0.3333
RS = 1
VJ = 0.6
TT = 100n
4/7
EMIF10-COM01C1
Figure 10: Ordering Information Scheme
EMIF yy - xxx zz Cx
EMI Filter
Number of lines
Information
x = resistance value (Ohms)
z = capacitance value / 10(pF)
or
3 letters = application
2 digits = version
Package
C = Coated Flip-Chip
x = 1: 500µm, Bump = 315µm
Figure 11: FLIP-CHIP Package Mechanical Data
500µm ± 50
315µm ± 50
695µm ± 70
Figure 12: Foot print recommendations
O
so
b
te
le
r
P
uc
od
s)
t(
bs
-O
2.64mm ± 50µm
et
l
o
500µm ± 50
P
e
od
r
s)
t(
uc
2.64mm ± 50µm
Figure 13: Marking
545
Dot, ST logo
xx = marking
z = packaging location
yww = datecode
(y = year
ww = week)
400
545
Copper pad Diameter :
250µm recommended , 300µm max
Solder stencil opening : 330µm
Solder mask opening recommendation :
340µm min for 315µm copper pad diameter
x x z
y ww
100
230
All dimensions in µm
5/7
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