ADVANCE INFORMATION
AS8nvLC512K32
512K x 32 Module nvSRAM
3.3V
High Speed SRAM with
Non-Volatile Storage
FEATURES
•
-55
o
C to 125
o
C Operation
•
True non-volatile SRAM (no batteries)
•
20 ns, 25 ns, and 45 ns access times
•
Automatic STORE on power down with only a small
capacitor
nvSRAM
AVAILABLE AS MILITARY
SPECIFICATIONS
• Military Processing (MIL-STD-883C para 1.2.2)
•
Temperature Range -55C to 125C
PIN ASSIGNMENT
(Top View)
68 Lead CQFP (Q)
VCAP
A0
A1
A2
A3
A4
A5
CE3\
GND
CE4\
WE1\
A6
A7
A8
A9
A10
Vcc
•
•
•
•
•
•
•
RECALL to SRAM initiated by software or power up
Infinite Read, Write, and Recall cycles
200,000 STORE cycles to QuantumTrap
20 year data retention
Single 3.3V +/- 0.3V operation
Ceramic Hermetic 68 Quad Flat Pack
-Matches compatible pinout footprint of SRAM & EEPROM
Module
•
68 Ceramic Quad Flat Pack
68 Ceramic Quad Flat Pack
Timing (Cycle Time)
45ns
25ns
20ns
Operating Temperature Ranges
-Industrial Temp (-40°C to 85° C)
-Enhanced Temp (-40°C to 105° C)
-Military Temp (-55°C to 125°C)
-Military Processing (-55°C to 125°C)
Q
QB
-45
-25
-20
IT
ET
XT
MIL
•
PINOUT / BLOCK DIAGRAM
Vcc
A11
A12
A13
A14
A15
A16
CE1\
OE\
CE2\
A17
WE2\
WE3\
WE4\
A18
NC
HSB\
CE
OPTIONS
MARKING
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
GND
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
STORE to QuantumTrap
®
nonvolatile elements initiated by
software, device pin, or AutoStore
®
on power down
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
GND
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
M4
M3
M2
M1
VCAP
•
HSB
1
CE
CE
FUNCTIONAL DESCRIPTION
The AS8nvLC512K32 is a fast static RAM, with a nonvolatile element
in each memory cell. The memory is organized as 512K bytes of 8
bits for each of 4 die to form 512Kx32. The embedded nonvolatile
elements incorporate QuantumTrap technology, producing the world’s
most reliable nonvolatile memory. The SRAM provides infinite read
and write cycles, while independent nonvolatile data resides in the
highly reliable QuantumTrap cell. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place automatically
at power down. On power up, data is restored to the SRAM (the
RECALL operation) from the nonvolatile memory. Both the STORE
and RECALL operations are also available under software control.
CE
Notes:
1. HSB\ signal is wired to all 4 die in module. This can be left open if
not used.
AS8nvLC512K32
Rev. 0.8 10/10
Micross Components reserves the right to change products or specifications without notice.
1
ADVANCE INFORMATION
AS8nvLC512K32
Pin Name
A0 – A18
DQ0 – DQ7
DQ0 – DQ15
DQ16 DQ23
DQ24 DQ31
WE\
1 4
CE\
1 4
OE\
V
SS
V
CC
HSB\
I/O Type
Input
Description
Address Inputs Used to Select one of the 524,288 32 bit words of the nvSRAM.
nvSRAM
Input/Output Bidirectional Data I/O Lines for die M1 (DQ0 7), M2 (DQ8 15), M3 (DQ16 23), M4 (DQ 24 31)
Write Enable Input, Active LOW. When selected LOW, data on the I/O pins is written to the specific
address location.
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Output Enable, Active LOW. The active LOW OE\ input enables the data output buffers during read cycles.
I/O pins are tri stated on deasserting OE\ HIGH.
Ground for the Device. Must be connected to the ground of the system.
Input
Input
Input
Ground
Power Supply Power Supply Inputs to the Device.
Hardware Store Busy (HSB\). When LOW this output indicates that a hardware store is in progress. When
pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull up resistor
Input/Output
keeps this pin HIGH if not connected (connection optional). After each store operation HSB\ is driven
HIGH for short time with standard output high current.
AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
Power Supply
nonvolatile elements.
No Connect No Connect. This pin is not connected to the die.
V
CAP
NC
LOGIC BLOCK DIAGRAM
[1, 2, 3]
4x
4x
DQ0-DQ31
(1-4)
28
29
30
31
(1-4)
AS8nvLC512K32
Rev. 0.8 10/10
Micross Components reserves the right to change products or specifications without notice.
2
ADVANCE INFORMATION
AS8nvLC512K32
Device Operation
The
AS8nvLC512K32
nvSRAM is made up of two functional
components paired in the same physical cell. They are
a SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the SRAM
is transferred to the nonvolatile cell (the STORE operation), or from
the nonvolatile cell to the SRAM (the RECALL operation). Using
this unique architecture, all cells are stored and recalled in parallel.
During the STORE and RECALL operations, SRAM read and write
operations are inhibited. The
AS8nvLC512K32
supports infinite reads
and writes similar to a typical SRAM. In addition, it provides infinite
RECALL operations from the nonvolatile cells and up to 200K STORE
operations. See the Truth Table For SRAM Operations for a complete
description of read and write modes.
Figure 2 shows the proper connection of the storage capacitor (V
CAP
)
for automatic store operation. Refer to DC Electrical Characteristics
for the size of V
CAP
. The voltage on
the V
CAP
pin is driven to V
CC
by a regulator on the chip. A pull up should be placed on WE\ to hold
it inactive during power up. This pull up is effective only if the WE\
signal is tri-state during power up. Many MPUs tri-state their controls
on power up. This should be verified when using the pull up. When
the nvSRAM comes out of power-on-recall, the MPU must be active
or the WE\ held inactive until the MPU comes out of reset.
To reduce unnecessary nonvolatile stores, AutoStore and hardware
store operations are ignored unless at least one write operation has
taken place since the most recent STORE or RECALL cycle. Software
initiated STORE cycles are performed regardless of whether a write
operation has taken place. The HSB\ signal is monitored by the system
to detect if an AutoStore cycle is in progress.
Figure 2. AutoStore Mode
Vcc
nvSRAM
SRAM Read
The
AS8nvLC512K32
performs a read cycle when CE\ and OE\ are
LOW and WE\ and HSB\ are HIGH. The address specified on pins
A0-18 determines which of the 524,288 data bytes. When the read is
initiated by an address transition, the outputs are valid after a delay
of t
AA
(read cycle 1). If the read is initiated by CE\ or OE\, the outputs
are valid at t
ACE
or at t
DOE
, whichever is later (read cycle 2). The data
output repeatedly responds to address changes within the t
AA
access
time without the need for transitions on any control input pins. This
remains valid until another address change or until CE\ or OE\ is
brought HIGH, or WE\ or HSB\ is brought LOW.
0.1uF
10kOhm
Vcc
1-4
WE
V
CAP
SRAM Write
A write cycle is performed when CE\ and WE\ are LOW and HSB\
is HIGH. The address inputs must be stable before entering the write
cycle and must remain stable until CE\ or WE\ goes HIGH at the end
of the cycle. The data on the common I/O pins DQ0–31 are written into
the memory if the data is valid t
SD
before the end of a WE\ controlled
write or before the end of an CE\ controlled write. It is recommended
that OE\ be kept HIGH during the entire write cycle to avoid data bus
contention on common I/O lines. If OE\ is left LOW, internal circuitry
turns off the output buffers tHZWE after WE\ goes LOW.
V
SS
V
CAP
Hardware STORE Operation
The AS8nvLC512K32 provides the HSB\
6
pin to control and
acknowledge the STORE operations. Use the HSB\ pin to request
a hardware STORE cycle. When the HSB\ pin is driven LOW, the
AS8nvLC512K32 conditionally initiates a STORE operation after
t
DELAY
. An actual STORE cycle only begins if a write to the SRAM
has taken place since the last STORE or RECALL cycle. The HSB\
pin also acts as an open drain driver that is internally driven LOW to
indicate a busy condition when the STORE (initiated by any means)
is in progress.
SRAM write operations that are in progress when HSB\ is driven LOW
by any means are given time to complete before the STORE operation
is initiated. After HSB\ goes LOW, the AS8nvLC512K32 continues
SRAM operations for tDELAY. If a write is in progress when HSB\
is pulled LOW it is enabled a time, t
DELAY
to complete. However, any
SRAM write cycles requested after HSB\ goes LOW are inhibited
until HSB\ returns HIGH. In case the write latch is not set, HSB\ is
not driven LOW by the AS8nvLC512K32. But any SRAM read and
write cycles are inhibited until HSB\ is returned HIGH by MPU or
other external source.
During any STORE operation, regardless of how it is initiated, the
AS8nvLC512K32 continues to drive the HSB\ pin LOW, releasing
it only when the STORE is complete. When the STORE operation is
completed, the AS8nvLC512K32 remains disabled until the HSB\ pin
returns HIGH. Leave the HSB\ unconnected if it is not used..
AutoStore Operation
The
AS8nvLC512K32
stores data to the nvSRAM using one of the
following three storage operations: Hardware Store activated by
HSB\; Software Store activated by an address sequence; AutoStore
on device power down. The AutoStore operation is a unique feature
of QuantumTrap technology and is enabled by default on the
AS8nvLC512K32.
During a normal operation, the device draws current from V
CC
to charge
a capacitor connected to the V
CAP
pin. This stored charge is used by the
chip to perform a single STORE operation. If the voltage on the V
CC
pin drops below V
SWITCH
, the part automatically disconnects the V
CAP
pin from V
CC
. A STORE operation is initiated with power provided
by the V
CAP
capacitor.
Note: If the capacitor is not connected to V
CAP
pin, AutoStore must be
disabled using the soft sequence specified in Preventing AutoStore on
page 5. In case AutoStore is enabled without a capacitor on V
CAP
pin,
the device attempts an AutoStore operation without sufficient charge
to complete the Store. This may corrupt the data stored in nvSRAM.
AS8nvLC512K32
Rev. 0.8 10/10
Micross Components reserves the right to change products or specifications without notice.
3
ADVANCE INFORMATION
AS8nvLC512K32
Hardware RECALL (Power Up)
During power up or after any low power condition (VCC< VSWITCH),
an internal RECALL request is latched. When VCC again exceeds
the sense voltage of VSWITCH, a RECALL cycle is automatically
initiated and takes tHRECALL to complete. During this time, HSB\
is driven LOW by the HSB\ driver.
The software sequence may be clocked with CE\ controlled reads
or OE\ controlled reads, with WE\ kept HIGH for all the six READ
sequences. After the sixth address in the sequence is entered, the
STORE cycle commences and the chip is disabled. HSB\ is driven
LOW. After the tSTORE cycle time is fulfilled, the SRAM is activated
again for the read and write operation.
nvSRAM
Software STORE
Transfer data from the SRAM to the nonvolatile memory with a
software address sequence. The AS8nvLC512K32 software STORE
cycle is initiated by executing sequential CE\ controlled read cycles
from six specific address locations in exact order. During the STORE
cycle an erase of the previous nonvolatile data is
fi
rst performed,
followed by a program of the nonvolatile elements. After a STORE
cycle is initiated, further input and output are disabled until the cycle
is completed.
Because a sequence of READs from specific addresses is used for
STORE initiation, it is important that no other read or write accesses
intervene in the sequence, or the sequence is aborted and no STORE
or RECALL takes place.
To initiate the software STORE cycle, the following read
sequence must be performed.
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8FC0 Initiate STORE Cycle
Software RECALL
Transfer the data from the nonvolatile memory to the SRAM with
a software address sequence. A software RECALL cycle is initiated
with a sequence of read operations in a manner similar to the software
STORE initiation. To initiate the RECALL cycle, the following
sequence of CE\ controlled read operations must be performed.
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4C63 Initiate RECALL Cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared; then, the nonvolatile information is transferred into the
SRAM cells. After the tRECALL cycle time, the SRAM is again ready
for read and write operations. The RECALL operation does not alter
the data in the nonvolatile elements.
Mode Selection
CE\
1 4
H
L
L
L
WE\
1 4
X
H
L
H
OE\
X
L
X
L
13
A15 A0
X
X
X
7
Mode
Not Selected
Read SRAM
Write SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Disable
I/O
0 31
Output High Z
Output Data
Input Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Power
Standby
Active
Active
Active
8
Notes
7. While there are 19 address lines on the AS8nvLC512K32, only the 13 address lines (A
14
- A
2
) are used to control software modes. Rest of the address lines are
don’t care.
8. The six consecutive address locations must be in the order listed. WE\ must be HIGH during all six cycles to enable a nonvolatile cycle.
13.WE\ must be HIGH during SRAM read cycles.
AS8nvLC512K32
Rev. 0.8 10/10
Micross Components reserves the right to change products or specifications without notice.
4
ADVANCE INFORMATION
AS8nvLC512K32
Mode Selection
(continued)
CE\
1 4
L
WE\
1 4
H
OE\
13
L
A15 A0
7
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Mode
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Enable
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Store
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
Recall
I/O
0 31
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Power
Active
8
nvSRAM
L
H
L
Active I
CC2 8
L
H
L
Active
8
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore disable
sequence. A sequence of read operations is performed in a manner
similar to the software STORE initiation. To initiate the AutoStore
disable sequence, the following sequence of CE\ controlled read
operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8B45 AutoStore Disable
The AutoStore is re-enabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a manner
similar to the software RECALL initiation. To initiate the AutoStore
enable sequence, the following sequence of CE\ controlled read
operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4B46 AutoStore Enable
If the AutoStore function is disabled or re-enabled, a manual STORE
operation (hardware or software) must be issued to save the AutoStore
state through subsequent power down cycles. The part comes from the
factory with AutoStore enabled.
Data Protection
The AS8nvLC512K32 protects data from corruption during
low voltage conditions by inhibiting all externally initiated
STORE and write operations. The low voltage condition is detected
when VCC < VSWITCH. If the AS8nvLC512K32 is in a write mode
(both CE\ and WE\ are LOW) at power up, after a RECALL or STORE,
the write is inhibited until the SRAM is enabled after tLZHSB (HSB\
to output active). This protects against inadvertent writes during power
up or brown out conditions.
AS8nvLC512K32
Rev. 0.8 10/10
Micross Components reserves the right to change products or specifications without notice.
5
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