IDT821054
Programmable Quad PCM CODEC
Preliminary Data Sheet, March 2001 (Ver 1.0)
File No. IDT821054DS(L)
7654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
7654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
7654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
7654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
7654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Features
♦
♦
♦
♦
Description
The IDT821054 is a feature rich, single-chip, programmable
4 channel PCM CODEC with on-chip filters. Besides the
µ-
Law/A-Law companding and Linear Coding/decoding (14
effective bits + 2 extra sign bits) , IDT821054 also provides 1
FSK generator(can be used for Caller-ID message sending),
2 programmable Tone generators per channel (which can
also generate ring signals) together with 2 programmable
chopper clocks for SLIC.
The digital filters in IDT821054provide the necessary transmit
and receive filtering for voice telephone circuit to interface
with time-division multiplexed systems. An integrated
programmable DSP realizes AC Impedance Matching,
Transhybrid Balance, Frequency Response Correction and
Gain Setting functions. The IDT821054 supports 2 PCM
buses with programmable sampling edge, which allows an
extra delay of up to 7 clocks. Once the delay is determined,
it is effective to all four channels of IDT821054. The device
also provides 7 signaling pins to SLIC on per channel basis.
The IDT821054 has a MPI interface and supports both
Compressed and Linear data format.
The device also offers strong test capability with several
analog/digital loop-backs and level metering function. It brings
convenience to system maintenance and diagnosis.
A unique feature of ‘Hardware Ring Trip’ is implemented in
IDT821054. When off-hook signal is detected, IDT821054
can reverse an output pin to stop ringing immediately.
The IDT821054 can be used in digital telecommunication
applications such as Central Office Switch, PBX, DLC and
Integrated Access Unit (IAD), i.e. VoIP and VoDSL.
4 channel CODEC with on-chip digital filters
Software Selectable A/µ-law, Linear Code conversion
Meets ITU-T G.711 - G.714 requirements
Programmable digital filter adapting to system
demands:
- AC impedance matching
- Transhybrid Balance
- Frequency response correction
- Gain Setting
♦
♦
Support two programmable PCM buses
Flexible PCM interface with up to 128 programmable
time slots, data rate from 512 kbits/s to 8.192 Mbits/s
MPI control interface
Broadcast mode for coefficient setting
7 SLIC signaling pins (including 2 debounced pins) per
channel
Fast hardware ring trip mechanism
Two programmable tone generators per channel for
testing,ringing and DTMF generating
FSK generator
Two programmable chopper clocks
Master clock frequency selectable: 1.536 MHz, 1.544
MHz, 2.048 MHz, 3.072 MHz, 3.088 MHz, 4.096 MHz,
6.144 MHz, 6.176 MHz or 8.192 MHz
Advanced test capabilities
- 3 analog loop back tests
- 5 digital loop back tests
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
- Level metering function
High analog driving capability (300
Ω ΑC
)
TTL and CMOS compatible digital I/O
CODEC identification
+5 V single power supply
Low power consumption
Operating temperature range: -40 °C to +85 °C
Package available:
IDT821054-XQ 64 pin PQFP
Integrated Device Technology, Inc.
IDT821054
Programmable Quad PCM CODEC
Pin Description
Name
GNDA
1
GNDA
2
GNDA
3
GNDA
4
GNDD
VDDA
12
VDDA
34
VDDB
Type
-
Pin Number
50
54
59
63
21
52
61
57
Description
Analog Ground.
All ground pins should be connected together.
-
-
-
CNF
VIN1-4
VOUT1-4
-
I
O
56
49, 55, 58, 64
51, 53, 60, 62
Digital Ground.
All digital signals are referred to this pin.
+5V Analog Power Supply.
These pins should be connected to ground via a 0.1µF capacitor. All power
supply pins should be connected together.
+5V Analog Power Supply.
This pin should be connected to ground via a 0.1µF capacitor. All power
supply pins should be connected together.
Capacitor Noise Filter
This pin should be connected to ground via a 0.22
µF
capacitor.
Analog Voice Inputs.
These pins should be connected with the SLIC via a capacitor (0.22
µF).
Voice Frequency Receiver Outputs.
These pins can drive 300
Ω
AC load. It allows the direct driving of
transformer.
SLIC signalling Inputs with de-bounced function for Channel 1-4.
SI1_(1-4)
SI2_(1-4)
SB1_(1-4)
SB2_(1-4)
SB3_(1-4)
SO1_(1-4)
SO2_(1-4)
DX1
DX2
DR1
I
36, 47, 2, 13
35, 48, 1, 14
39, 44, 5, 10
38, 45, 4, 11
37, 46, 3, 12
41, 42, 7, 8
40, 43, 6, 9
I/O
Bidirectional SLIC Signalling I/Os for Channel 1-4, can be programmed
as Input or Output.
O
SLIC Signalling Outputs for Channel 1-4.
O
O
I
26
29
27
DR2
I
30
FS
I
31
BCLK
I
32
TSX1
0
25
Transmit PCM Data Output, PCM high-way One .
Transmit PCM Data to PCM-High-way One. This pin is tri-state output pin.
Transmit PCM Data Output, PCM high-way Two .
Transmit PCM Data to PCM-High-way Two. This pin is tri-state output pin.
Receive PCM Data Input, PCM high-way One.
PCM data is shifted into DR1 or DR2 following the BCLK. PCM data can be
selected to input from DR1 and DR2.
Receive PCM Data Input, PCM high-way Two.
PCM data is shifted into DR1 or DR2 following the BCLK. PCM data can be
selected to input from DR1 and DR2
Frame Synchronisation
FS is an 8 kHz synchronisation clock that identifies the beginning of the
PCM frame.
Bit Clock.
This pin clocks out the PCM data on DX1 or DX2 pin. It may vary from
512kHz to 8.192 MHz, and is required to be synchronous with FS.
Transmit Output Indicator.
This pin becomes low when data is transmitted via DX1, open-drain.
This pin becomes low when data is transmitted via DX2, open-drain.
TSX2
28
Page-4
IDT821054
Programmable Quad PCM CODEC
Pin Description(continued)
Name
CS
CI
CO
Type
I
I
O
Pin Number
17
19
20
Description
Chip Select.
A low level on this pin enables the Serial Control Interface.
Serial Control Interface Data Input.
µ-Controller
interface, Control data input, CCLK determines the data rate.
Serial Control Interface Data Tri-State Output.
µ-Controller
interface, control data output pin, CCLK determines the data
rate.
Serial Control Interface Clock .
This is the clock for Serial Control Interface. It can be up to 8.192 MHz.
Master Clock Input.
Master clock provides the clock for DSP. It can be 1.536 MHz, 1.544 MHz,
2.048 MHz, 3.072MHz, 3.088MHz, 4.096 MHz, 6.144MHz, 6.176MHz or
8.192 MHz.
Reset Input.
Forces the device to default mode. Active low.
Interrupt Output Pin.
Active high interrupt signal for ch1-ch2. It reflects the changes on SLIC pins.
Interrupt Output Pin.
Active high interrupt signal for ch3-ch4. It reflects the changes on SLIC pins.
Chopper Clock Output.
Provides a programmable (2 -28 ms) output signal synchronous to MCLK.
Chopper Clock Output.
Provides a programmable 256 kHz, or 512 kHz or 16.384 MHz output signal
synchronous to MCLK.
CCLK
MCLK
I
I
18
22
RESET
INT
12
INT
34
CHCLK1
CHCLK2
I
O
O
O
O
23
34
15
33
16
Page-5
京公网安备 11010802033920号
EEWORLD
