256MB, 512MB Unbuffered DIMMs
DDR2 SDRAM
DDR2 Unbuffered SDRAM MODULE
240pin Unbuffered Module based on 256Mb F-die
64/72-bit Non-ECC/ECC
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.3 Aug. 2005
256MB, 512MB Unbuffered DIMMs
DDR2 Unbuffered DIMM Ordering Information
Part Number
M378T3253FG(Z)3-CE6/D5/CC
M378T3253FG(Z)0-CE6/D5/CC
M378T6453FG(Z)3-CE6/D5/CC
M378T6453FG(Z)0-CE6/D5/CC
M391T3253FG(Z)3-CE6/D5/CC
M391T3253FG(Z)0-CE6/D5/CC
M391T6453FG(Z)3-CE6/D5/CC
M391T6453FG(Z)0-CE6/D5/CC
Density
256MB
256MB
512MB
512MB
256MB
256MB
512MB
512MB
Organization
32Mx64
32Mx64
64Mx64
64Mx64
x72 ECC
32Mx72
32Mx72
64Mx72
64Mx72
32Mx8(K4T56083QF)*9
32Mx8(K4T56083QF)*9
32Mx8(K4T56083QF)*18
32Mx8(K4T56083QF)*18
Component Composition
32Mx8(K4T56083QF)*8
32Mx8(K4T56083QF)*8
32Mx8(K4T56083QF)*16
32Mx8(K4T56083QF)*16
DDR2 SDRAM
Number of Rank
1
1
2
2
1
1
2
2
Height
30mm
30mm
30mm
30mm
30mm
30mm
30mm
30mm
x64 Non ECC
Note: “Z” of Part number(11th digit) stand for Lead-free products.
Note: “3” of Part number(12th digit) stand for Dummy Pad PCB products.
Features
• Performance range
E6(DDR2-667)
Speed@CL3
Speed@CL4
Speed@CL5
CL-tRCD-tRP
400
533
667
5-5-5
D5(DDR2-533)
400
533
-
4-4-4
CC(DDR2-400)
400
400
-
3-3-3
Unit
Mbps
Mbps
Mbps
CK
• JEDEC standard 1.8V ± 0.1V Power Supply
• V
DDQ
= 1.8V ± 0.1V
• 200 MHz f
CK
for 400Mb/sec/pin, 267MHz f
CK
for 533Mb/sec/pin, 333MHz f
CK
for 667Mb/sec/pin
• 4 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5
• Programmable Additive Latency: 0, 1 , 2 , 3 and 4
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Average Refresh Period 7.8us at lower than a T
CASE
85°C, 3.9us at 85°C < T
CASE
< 95
°C
-
support High Temperature Self-Refresh rate enable feature
• Package: 60ball FBGA - 32Mx8
• All of Lead-free products are compliant for RoHS
Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.
Address Configuration
Organization
32Mx8(256Mb) based Module
Row Address
A0-A12
Column Address
A0-A9
Bank Address
BA0-BA1
Auto Precharge
A10
Rev. 1.3 Aug. 2005
256MB, 512MB Unbuffered DIMMs
x64 DIMM Pin Configurations (Front side/Back side)
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DDR2 SDRAM
Pin
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
Front
V
REF
V
SS
DQ0
DQ1
V
SS
DQS0
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1
DQS1
V
SS
NC
NC
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2
DQS2
V
SS
DQ18
Pin
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Back
V
SS
DQ4
DQ5
V
SS
DM0
NC
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1
NC
V
SS
CK1
CK1
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DM2
NC
V
SS
DQ22
DQ23
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Front
DQ19
V
SS
DQ24
DQ25
V
SS
DQS3
DQS3
V
SS
DQ26
DQ27
V
SS
NC
NC
V
SS
NC
NC
V
SS
NC
NC
V
SS
V
DDQ
CKE0
V
DD
NC
NC
V
DDQ
A11
A7
V
DD
A5
Pin
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Back
V
SS
DQ28
DQ29
V
SS
DM3
NC
V
SS
DQ30
DQ31
V
SS
NC
NC
V
SS
NC
NC
V
SS
NC
NC
V
SS
V
DDQ
CKE1
V
DD
NC
NC
V
DDQ
A12
A9
V
DD
A8
A6
Front
A4
V
DDQ
A2
V
DD
Pin
181
182
183
184
KEY
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
Back
V
DDQ
A3
A1
V
DD
CK0
CK0
V
DD
A0
V
DD
BA1
V
DDQ
RAS
S0
V
DDQ
ODT0
NC
V
DD
V
SS
DQ36
DQ37
V
SS
DM4
NC
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
Pin
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Front
V
SS
DQS5
DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
SA2
NC,
V
SS
TEST
2
Pin
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Back
DM5
NC
V
SS
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
CK2
CK2
V
SS
DM6
NC
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DM7
NC
V
SS
DQ62
DQ63
V
SS
VDDSPD
SA0
SA1
V
SS
V
SS
V
DD
NC
V
DD
A10/AP
BA0
V
DDQ
WE
CAS
V
DDQ
S1
ODT1
V
DDQ
V
SS
DQ32
DQ33
V
SS
DQS4
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
DQS6
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DQS7
DQS7
V
SS
DQ58
DQ59
V
SS
SDA
SCL
NC = No Connect, RFU = Reserved for Future Use
1. Pin173 Pin174 are reserved for 2Gb/4Gb comp. base Unbuffered DIMM.
2. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products (DIMMs.)
Rev. 1.3 Aug. 2005
256MB, 512MB Unbuffered DIMMs
x72 DIMM Pin Configurations (Front side/Back side)
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DDR2 SDRAM
Pin
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
Front
V
REF
V
SS
DQ0
DQ1
V
SS
DQS0
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1
DQS1
V
SS
NC
NC
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2
DQS2
V
SS
DQ18
Pin
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Back
V
SS
DQ4
DQ5
V
SS
DM0
NC
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1
NC
V
SS
CK1
CK1
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DM2
NC
V
SS
DQ22
DQ23
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Front
DQ19
V
SS
DQ24
DQ25
V
SS
DQS3
DQS3
V
SS
DQ26
DQ27
V
SS
CB0
CB1
V
SS
DQS8
DQS8
V
SS
CB2
CB3
V
SS
V
DDQ
CKE0
V
DD
NC
NC
V
DDQ
A11
A7
V
DD
A5
Pin
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Back
V
SS
DQ28
DQ29
V
SS
DM3
NC
V
SS
DQ30
DQ31
V
SS
CB4
CB5
V
SS
DM8
NC
V
SS
CB6
CB7
V
SS
V
DDQ
CKE1
V
DD
NC
NC
V
DDQ
A12
A9
V
DD
A8
A6
Front
A4
V
DDQ
A2
V
DD
KEY
V
SS
V
SS
V
DD
NC
V
DD
A10/AP
BA0
V
DDQ
WE
CAS
V
DDQ
S1
ODT1
V
DDQ
V
SS
DQ32
DQ33
V
SS
DQS4
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
Pin
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
Back
V
DDQ
A3
A1
V
DD
CK0
CK0
V
DD
A0
V
DD
BA1
V
DDQ
RAS
S0
V
DDQ
ODT0
NC
V
DD
V
SS
DQ36
DQ37
V
SS
DM4
NC
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
Pin
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Front
V
SS
DQS5
DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
SA2
NC, TEST
2
V
SS
DQS6
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DQS7
DQS7
V
SS
DQ58
DQ59
V
SS
SDA
SCL
Pin
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Back
DM5
NC
V
SS
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
CK2
CK2
V
SS
DM6
NC
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DM7
NC
V
SS
DQ62
DQ63
V
SS
VDDSPD
SA0
SA1
NC = No Connect, RFU = Reserved for Future Use
1. Pin173 Pin174 are reserved for 2Gb/4Gb comp. base Unbuffered DIMM.
2. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products (DIMMs.)
Pin Description
Pin Name
A0-A12
BA0, BA1
RAS
CAS
WE
S0, S1
CKE0,CKE1
ODT0, ODT1
DQ0 - DQ63
CB0 - CB7
DQS0 - DQS8
DM(0-8)
DQS0-DQS8
Description
DDR2 SDRAM address bus
DDR2 SDRAM bank select
DDR2 SDRAM row address strobe
DDR2 SDRAM column address strobe
DDR2 SDRAM wirte enable
DIMM Rank Select Lines
DDR2 SDRAM clock enable lines
On-die termination control lines
DIMM memory data bus
DIMM ECC check bits
DDR2 SDRAM data strobes
DDR2 SDRAM data masks
DDR2 SDRAM differential data strobes
Pin Name
CK0, CK1, CK2
CK0, CK1, CK2
SCL
SDA
SA0-SA2
V
DD
*
V
DDQ
*
V
REF
V
SS
V
DD
SPD
NC
RESET
TEST
Description
DDR2 SDRAM clocks (positive line of differential pair)
DDR2 SDRAM clocks (negative line of differential pair)
I
2
C serial bus clock for EEPROM
I
2
C serial bus data line for EEPROM
I
2
C serial address select for EEPROM
DDR2 SDRAM core power supply
DDR2 SDRAM I/O Driver power supply
DDR2 SDRAM I/O reference supply
Power supply return (ground)
Serial EEPROM positive power supply
Spare Pins(no connect)
Not used on UDIMM
Used by memory bus analysis tools (unused on memory
DIMMs)
* The VDD and VDDQ pins are tied to the single power-plane on PCB.
Rev. 1.3 Aug. 2005
256MB, 512MB Unbuffered DIMMs
Input/Output Functional Description
Symbol
CK0-CK2
CK0-CK2
CKE0-CKE1
S0-S1
RAS, CAS, WE
ODT0-ODT1
V
REF
V
DDQ
BA0-BA1
Type
Input
Input
Input
Input
Input
Supply
Supply
Input
Function
DDR2 SDRAM
CK and CK are differential clock inputs. All the SDRAM addr/cntl inputs are sampled on the crossing of positive edge of
CK and negative edge of CK. Output (read) data is reference to the crossing of CK and CK (Both directions of crossing)
Activates the SDRAM CK signal when high and deactivates the CK Signal When low. By deactivating the clocks, CKE
low initiates the Powe Down mode, or the Self-Refresh mode
Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the
command decoder is disbled, new command are ignored but previous operations continue. This signal provides for exter-
nal rank selection on systems with multiple ranks
RAS, CAS, and WE (
ALONG WITH
CS) define the command being entered.
When high, termination resistance is enabled for all DQ, DQ and DM pins, assuming the function is enabled in the
Extended Mode Register Set (EMRS).
Reference voltage for SSTL 18 inputs.
Power supply for the DDR II SDRAM output buffers to provide improved noise immunity. For all current DDR2 unbuffered
DIMM designs, VDDQ shares the same power plane as VDD pins.
Selects which SDRAM BANK of four is activated.
During a Bank Activate command cycle, Address input defines the row address (RA0-RA13)
During a Read or Write command cycle, Address input defines the colum address, In addition to the column address, AP
is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is
selected and BA0, BA1 defines the bank to be precharged. If AP is low, autoprecharge is disbled. During a precharge
command cycle, AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If AP is high, all banks
will be precharged regardless of the state of BA0, BA1. If AP is low, BA0, BA1are used to define which bank to pre-
charge.
Data and Check Bit Input/Output pins.
DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with that input data
during a write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches
the DQ and DQS loading.
Power and ground for DDR2 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to V
DD
/V
DDQ
planes on
these modules.
Data strobe for input and output data. For Rawcards using x16 orginized DRAMs DQ0-7 connect to the LDQS pin of the
DRAMs and DQ8-17 connect to the UDQS pin of the DRAM
These signals and tied at the system planar to either V
SS
or V
DD
to configure the serial SPD EERPOM address range.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the
SDA bus line to VDD to act as a pullup on the system board.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time
to VDD to act as a pullup onthe system board.
Power supply for SPD EEPROM. This supply is separate from the V
DD
/V
DDQ
power plane. EEPROM supply is operable
from 1.7V to 3.6V.
A0-A13
Input
DQ0-DQ63
CB0-CB7
DM0-DM8
V
DD
,V
SS
DQS0-DQS8
DQS0-DQS8
SA0-SA2
SDA
SCL
V
DD
SPD
In/Out
Input
Supply
In/Out
Input
In/Out
Input
Supply
Rev. 1.3 Aug. 2005
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EEWORLD
