MAX911_E.......................................................-40°C to +85°C
MAX911_A .....................................................-40°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
SOT23-8
PACKAGE CODE
Outline Number
Land Pattern Number
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θ
JA
)
Junction to Case (θ
JC
)
195.80°C/W
70°C/W
S8-2/S8+2
21-0041
90-0096
170°C/W
40°C/W
136°C/W
38°C/W
T822CY+2
21-100341
90-100117
162°C/W
20°C/W
21-0078
90-0176
K8+1
SO-8
PACKAGE CODE
Outline Number
Land Pattern Number
Thermal Resistance, Single-Layer Board:
Junction to Ambient (θ
JA
)
Junction to Case (θ
JC
)
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θ
JA
)
Junction to Case (θ
JC
)
PACKAGE CODE
Outline Number
Land Pattern Number
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θ
JA
)
Junction to Case (θ
JC
)
TDFN-8
For the latest package outline information and land patterns (footprints), go to
www.maximintegrated.com/packages.
Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial.
www.maximintegrated.com
Maxim Integrated
│
2
MAX9111/MAX9113
Single/Dual LVDS Line Receivers with
Ultra-Low Pulse Skew in SOT23
Electrical Characteristics
(V
CC
= +3.0V to +3.6V, magnitude of input voltage, |V
ID
| = +0.1V to +1.0V, V
CM
= |V
ID
|/2 to (2.4V - (|V
ID
|/2)), T
A
= T
MIN
to T
MAX
.
Typical values are at V
CC
= +3.3V and T
A
= +25°C, unless otherwise noted.) (Notes 1, 2)
PARAMETER
Differential Input High Threshold
(Note 3)
Differential Input Low Threshold
(Note 3)
Differential Input Resistance
SYMBOL
V
TH
V
TL
R
DIFF
CONDITIONS
V
CM
= 0.05V, 1.2V, 2.75V at 3.3V
V
CM
= 0.05V, 1.2V, 2.75V at 3.3V
V
CM
= 0.2V or 2.2V, V
ID
= ±0.4V,
V
CC
= 0 or 3.6V
V
ID
= +200mV
Output High Voltage (OUT_)
V
OH
I
OH
= -4mA
Inputs shorted, undriven
100Ω parallel
termination, undriven
-100
5
2.7
2.7
2.7
0.4
-100
-120
4.2
8.7
8.7
6
11
16
mA
mA
V
18
MIN
TYP
MAX
100
UNITS
mV
mV
kΩ
Output Low Voltage (OUT_)
Output Short-Circuit Current
V
OL
I
OS
I
OL
= 4mA, V
ID
= -200mV
V
ID
= +200mV, V
OUT
_ = 0
MAX9113ATA/VY+
MAX9111
MAX9113
MAX9113ATA/VY+
No-Load Supply Current
I
CC
www.maximintegrated.com
Maxim Integrated
│
3
MAX9111/MAX9113
Single/Dual LVDS Line Receivers with
Ultra-Low Pulse Skew in SOT23
Switching Characteristics
PARAMETER
Differential Propagation Delay
High to Low
(V
CC
= +3.0V to +3.6V, T
A
= T
MIN
to T
MAX
. Typical values are at V
CC
= +3.3V and T
A
= +25°C, unless otherwise noted.) (Notes 4, 5, 6)
SYMBOL
t
PHLD
CONDITIONS
T
A
= +85°C
C
L
= 15pF, V
ID
= ±200mV, T
A
= +125°C
V
CM
= 1.2V (Figures 1, 2) T
A
= +125°C
MAX9113ATA/VY+
T
A
= +85°C
C
L
= 15pF, V
ID
= ±200mV, T
A
= +125°C
V
CM
= 1.2V (Figures 1, 2) T = +125°C
A
MAX9113ATA/VY+
MAX9113ATA/VY+
140
C
L
= 15pF, V
ID
= ±200mV, MAX9113ATA/VY+
V
CM
= 1.2V (Figures 1, 2)
MAX9113ATA/VY+
MAX9113ATA/VY+
T
A
= +85°C
Rise Time
t
TLH
C
L
= 15pF, V
ID
= ±200mV, T
A
= +125°C
V
CM
= 1.2V (Figures 1, 2) T = +125°C
A
(MAX9113ATA/VY+)
T
A
= +85°C
Fall Time
t
THL
C
L
= 15pF, V
ID
= ±200mV, T
A
= +125°C
V
CM
= 1.2V (Figures 1, 2)
T
A
= +125°C
(MAX9113ATA/VY+)
All channels
switching, C
L
= 15pF,
V
OL
(max) = 0.4V,
V
OH
(min) = 2.7V,
MAX9113ATA/VY+T
40% < duty cycle <
only
60% (Note 6)
250
300
MHz
300
0.6
0.6
MIN
1.0
TYP
1.77
MAX
2.5
3.0
3.5
1.0
1.68
2.5
3.0
3.5
90
300
1200
400
900
1
1200
1.5
2000
0.8
1.0
1.6
0.8
1.0
1.8
ns
ns
ps
ps
ns
ns
UNITS
ns
Differential Propagation Delay
Low to High
Differential Pulse Skew
|t
PLHD
- t
PHLD
| (Note 7)
Differential Channel-to-Channel
Skew; Same Device
(MAX9113 only) (Note 8)
Differential Part-to-Part Skew
(Note 9)
Differential Part-to-Part Skew
(MAX9113 only) (Note 10)
t
PLHD
ns
t
SKD1
t
SKD2
t
SKD3
t
SKD4
Maximum Operating Frequency
f
MAX
Note 1:
Note
Note
Note
Note
Note
Note
Note
Note
Note
Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at T
A
= +25°C.
2:
Current into the device is defined as positive. Current out of the devices is defined as negative. All voltages are referenced
to ground except V
TH
and V
TL
.
3:
Guaranteed by design, not production tested.
4:
AC parameters are guaranteed by design and characterization.
5:
C
L
includes probe and test jig capacitance.
6:
f
MAX
generator output conditions: t
R
= t
F
< 1ns (0 to 100%), 50% duty cycle, V
OH
= 1.3V, V
OL
= 1.1V.
7:
t
SKD1
is the magnitude difference of differential propagation delays in a channel. t
SKD1
= |t
PLHD
- t
PHLD
|.
8:
t
SKD2
is the magnitude difference of the t
PLHD
or t
PHLD
of one channel and the t
PLHD
or t
PHLD
of the other channel on
the same device.
9:
t
SKD3
is the magnitude difference of any differential propagation delays between devices at the same V
CC
and within 5°C
of each other.
10:
t
SKD4
, is the magnitude difference of any differential propagation delays between devices operating over the rated supply
and temperature ranges.
www.maximintegrated.com
Maxim Integrated
│
4
MAX9111/MAX9113
Single/Dual LVDS Line Receivers with
Ultra-Low Pulse Skew in SOT23
Test Circuit Diagrams
IN_+
GENERATOR
IN_-
R
C
L
50
Ω
50
Ω
OUT_
Figure 1. Receiver Propagation Delay and Transition Time Test Circuit
IN_-
0V DIFFERENTIAL
IN_+
t
PLHD
80%
50%
OUT_
20%
t
TLH
t
PHLD
80%
V
ID
= 200mV
+1.2V
+1.3V
+1.1V
V
OH
50%
20%
t
THL
V
OL
Figure 2. Receiver Propagation Delay and Transition Time Waveforms
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