UPD4516821AG5-A10B-9NF datasheet, PDF

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UPD4516821AG5-A10B-9NF: DescriptionSynchronous DRAM, 2MX8, 7ns, MOS, PDSO44, 0.400 INCH, PLASTIC, TSOP2-44; Categorystorage storage; File Size1MB，88 Pages; ManufacturerELPIDA; Websitehttp://www.elpida.com/en

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UPD4516821AG5-A10B-9NF Overview

Synchronous DRAM, 2MX8, 7ns, MOS, PDSO44, 0.400 INCH, PLASTIC, TSOP2-44

UPD4516821AG5-A10B-9NF Parametric

Parameter Name	Attribute value
Parts packaging code	TSOP2
package instruction	TSOP2,
Contacts	44
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	DUAL BANK PAGE BURST
Maximum access time	7 ns
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PDSO-G44
length	18.32 mm
memory density	16777216 bit
Memory IC Type	SYNCHRONOUS DRAM
memory width	8
Number of functions	1
Number of ports	1
Number of terminals	44
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	2MX8
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Certification status	Not Qualified
Maximum seat height	1.2 mm
self refresh	YES
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	MOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	DUAL
width	10.16 mm
Base Number Matches	1

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DATA SHEET

MOS INTEGRATED CIRCUIT

PD4516421A, 4516821A, 4516161A for Rev.P

16M-bit Synchronous DRAM

2-banks, LVTTL

Description

Features

•

Pulsed interface

• ×4, ×8, ×16

organization

Document No. E0122N10 (Ver.1.0)

(Previous No. M12939EJ3V0DS00)

Date Published May 2001 CP (K)

Printed in Japan

The

PD4516421A, 4516821A, 4516161A are high-speed 16,777,216-bit synchronous dynamic random-access

The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.

All inputs and outputs are synchronized with the positive edge of the clock.

The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).

These products are packaged in 44-pin TSOP (II) (× 4,

8) and 50-pin TSOP (II) (× 16).

memories, organized as 2,097,152

2, 1,048,576

2, 524,288

2 (word

bit

bank), respectively.

•

Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge

•

Possible to assert random column address in every cycle

•

Dual internal banks controlled by A11(Bank Select)

•

Byte control (×16) by LDQM and UDQM

•

Programmable Wrap sequence (Sequential / Interleave)

•

Programmable burst length (1, 2, 4, 8 and full page)

•

Programmable /CAS latency (2 and 3)

•

CBR (Auto) refresh and self refresh

•

Single 3.3 V

0.3 V power supply

•

2,048 refresh cycles / 32 ms

•

Automatic precharge and controlled precharge

•

LVTTL compatible inputs and outputs

•

Burst termination by Burst stop command and Precharge command

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for

availability and additional information.

Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.

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