UPD44644365F5-E50-FQ1-A datasheet, PDF

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UPD44644365F5-E50-FQ1-A: Description2MX36 DDR SRAM, 0.45ns, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165; Categorystorage storage; File Size371KB，40 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/; Environmental Compliance

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UPD44644365F5-E50-FQ1-A Overview

2MX36 DDR SRAM, 0.45ns, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165

UPD44644365F5-E50-FQ1-A Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	BGA
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	0.45 ns
Maximum clock frequency (fCLK)	200 MHz
I/O type	SEPARATE
JESD-30 code	R-PBGA-B165
memory density	75497472 bit
Memory IC Type	STANDARD SRAM
memory width	36
Number of terminals	165
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	2MX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
power supply	1.5/1.8,1.8 V
Certification status	Not Qualified
Minimum standby current	1.7 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Base Number Matches	1

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PRELIMINARY DATA SHEET

MOS INTEGRATED CIRCUIT

PD44644085, 44644095, 44644185, 44644365

72M-BIT DDR II SRAM SEPARATE I/O

2-WORD BURST OPERATION

Description

The

PD44644085 is a 8,388,608-word by 8-bit, the

PD44644095 is a 8,388,608-word by 9-bit, the

PD44644185 is a

4,194,304-word by 18-bit and the

PD44644365 is a 2,097,152-word by 36-bit synchronous double data rate static RAM

fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.

The

PD44644085,

PD44644095,

PD44644185 and

PD44644365 integrate unique synchronous peripheral circuitry

and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive edge of K

and K#.

These products are suitable for application which require synchronous operation, high speed, low voltage, high density

and wide bit configuration.

These products are packaged in 165-pin PLASTIC BGA.

Features

•

1.8

0.1 V power supply

•

165-pin PLASTIC BGA package (15 x 17)

•

HSTL interface

•

PLL circuitry for wide output data valid window and future frequency scaling

•

Separate independent read and write data ports

•

DDR read or write operation initiated each cycle

•

Pipelined double data rate operation

•

Separate data input/output bus

•

Two-tick burst for low DDR transaction size

•

Two input clocks (K and K#) for precise DDR timing at clock rising edges only

•

Two output clocks (C and C#) for precise flight time and clock skew matching-clock

and data delivered together to receiving device

•

Internally self-timed write control

•

Clock-stop capability. Normal operation is restored in 1,024 cycles after clock is resumed.

•

User programmable impedance output

•

Fast clock cycle time : 3.7 ns (270 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz)

•

Simple control logic for easy depth expansion

•

JTAG boundary scan

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with an NEC Electronics

sales representative for availability and additional information.

Document No. M18230EJ2V0DS00 (2nd edition)

Date Published February 2007 NS CP(N)

Printed in Japan

The mark <R> shows major revised points.

2006

The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.

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