RH80532NC021256 datasheet, PDF

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RH80532NC021256: DescriptionMicroprocessor, 32-Bit, 1500MHz, CMOS, CPGA478, MICRO, FLIP CHIP, PGA-478; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，94 Pages; ManufacturerIntel; Websitehttp://www.intel.com/; Environmental Compliance

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RH80532NC021256 Overview

Microprocessor, 32-Bit, 1500MHz, CMOS, CPGA478, MICRO, FLIP CHIP, PGA-478

RH80532NC021256 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Parts packaging code	PGA
package instruction	SPGA, PGA478,26X26,50
Contacts	478
Reach Compliance Code	unknown
ECCN code	3A001.A.3
Address bus width	36
bit size	32
boundary scan	YES
maximum clock frequency	100 MHz
External data bus width	64
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-CPGA-P478
length	35 mm
low power mode	YES
Number of terminals	478
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	SPGA
Encapsulate equivalent code	PGA478,26X26,50
Package shape	SQUARE
Package form	GRID ARRAY, SHRINK PITCH
power supply	1.3 V
Certification status	Not Qualified
Maximum seat height	3.28 mm
speed	1500 MHz
Maximum slew rate	27500 mA
Nominal supply voltage	1.3 V
surface mount	NO
technology	CMOS
Terminal form	PIN/PEG
Terminal pitch	1.27 mm
Terminal location	PERPENDICULAR
width	35 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR
Base Number Matches	1

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Mobile Intel



Celeron



Processor

on .13 Micron Process and in

Micro-FCPGA Package

Datasheet

November 2003

Order Number: 251308-006

Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any

patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Information

contained herein supersedes previously published specifications on these devices from Intel.

Actual system-level properties, such as skin temperature, are a function of various factors, including component placement, component power

characteristics, system power and thermal management techniques, software application usage and general system design. Intel is not responsible

for its customers' system designs, nor is Intel responsible for ensuring that its customers' products comply with all applicable laws and regulations.

Intel provides this and other thermal design information for informational purposes only. System design is the sole responsibility of Intel's customers,

and Intel's customers should not rely on any Intel-provided information as either an endorsement or recommendation of any particular system design

characteristics.

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual

property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability

whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to

fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not

intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The mobile Intel Celeron processor may contain design defects or errors known as errata which may cause the product to deviate from published

specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-

548-4725 or by visiting Intel’s website at http://www.intel.com

Intel, Celeron, and Intel NetBurst are registered trademarks or trademarks of Intel Corporation and its subsidiares in the United States and other

countries.

* Other brands and names may be claimed as property of others.

Mobile Intel

Celeron

Processor on .13 Micron Process

and in Micro-FCPGA Package Datasheet

Contents

Introduction...................................................................................................................................... 9

1.1

1.2

2.1

2.2

2.3

Terminology ........................................................................................................................ 10

References ......................................................................................................................... 10

FSB and GTLREF............................................................................................................... 11

Power and Ground Pins...................................................................................................... 11

Decoupling Guidelines........................................................................................................ 11

2.3.1 VCC Decoupling .................................................................................................... 12

2.3.2 FSB AGTL+ Decoupling ........................................................................................ 12

2.3.3 FSB Clock (BCLK[1:0]) and Processor Clocking ................................................... 12

Voltage Identification and Power Sequencing .................................................................... 13

2.4.1 Phase Lock Loop (PLL) Power and Filter .............................................................. 14

2.4.2 Catastrophic Thermal Protection ........................................................................... 16

Signal Terminations, Unused Pins and TESTHI[11:0] ........................................................ 16

FSB Signal Groups ............................................................................................................. 18

Asynchronous GTL+ Signals ..............................................................................................20

Test Access Port (TAP) Connection ................................................................................... 20

FSB Frequency Select Signals (BSEL[1:0]) ....................................................................... 20

Maximum Ratings ............................................................................................................... 21

Processor DC Specifications ..............................................................................................21

AGTL+ FSB Specifications ................................................................................................. 30

FSB AC Specifications........................................................................................................ 31

Processor AC Timing Waveforms....................................................................................... 36

FSB Clock (BCLK) Signal Quality Specifications and Measurement Guidelines................ 47

FSB Signal Quality Specifications and Measurement Guidelines ...................................... 48

FSB Signal Quality Specifications and Measurement Guidelines ...................................... 51

3.3.1 Overshoot/Undershoot Guidelines......................................................................... 51

3.3.2 Overshoot/Undershoot Magnitude ......................................................................... 51

3.3.3 Overshoot/Undershoot Pulse Duration .................................................................. 51

3.3.4 Activity Factor ........................................................................................................ 52

3.3.5 Reading Overshoot/Undershoot Specification Tables ........................................... 52

3.3.6 Conformance Determination to Overshoot/Undershoot Specifications.................. 53

Processor Pin-Out .............................................................................................................. 60

Mobile Intel Celeron Processor Pin Assignments ............................................................... 63

Alphabetical Signals Reference .......................................................................................... 79

Thermal Specifications ....................................................................................................... 88

6.1.1 Thermal Diode ....................................................................................................... 88

6.1.2 Thermal Monitor..................................................................................................... 89

Electrical Specifications ................................................................................................................. 11

2.4

2.5

2.6

2.7

2.8

2.9

2.10

2.11

2.12

2.13

2.14

3.1

3.2

3.3

FSB Signal Quality Specifications ................................................................................................. 47

Package Mechanical Specifications ..............................................................................................57

4.1

5.1

5.2

Pin Listing and Signal Definitions .................................................................................................. 63

Thermal Specifications and Design Considerations ...................................................................... 87

6.1

Mobile Intel

Celeron

Processor on .13 Micron Process

and in Micro-FCPGA Package Datasheet

Figures

VCCVID Pin Voltage and Current Requirements ....................................................................... 13

Typical VCCIOPLL, VCCA and VSSA Power Distribution.......................................................... 15

Phase Lock Loop (PLL) Filter Requirements............................................................................. 16

Illustration of VCC Static and Transient Tolerances (VID = 1.30 V) ........................................... 24

Illustration of Deep Sleep VCC Static and Transient Tolerances (VID Setting = 1.30 V) ........... 25

ITPCLKOUT[1:0] Output Buffer Diagram.................................................................................... 30

AC Test Circuit............................................................................................................................ 37

TCK Clock Waveform ................................................................................................................. 37

Differential Clock Waveform ....................................................................................................... 38

Differential Clock Crosspoint Specification ................................................................................. 39

FSB Common Clock Valid Delay Timings .................................................................................. 39

FSB Reset and Configuration Timings ....................................................................................... 40

Source Synchronous 2X (Address) Timings............................................................................... 40

Source Synchronous 4X Timings ............................................................................................... 41

Power Up Sequence.................................................................................................................. 42

Power Down Sequence .............................................................................................................. 42

Test Reset Timings..................................................................................................................... 43

THERMTRIP# to Vcc Timing ...................................................................................................... 43

FERR#/PBE# Valid Delay Timing............................................................................................... 43

TAP Valid Delay Timing.............................................................................................................. 44

ITPCLKOUT Valid Delay Timing.................................................................................................44

Stop Grant/Sleep/Deep Sleep Timing......................................................................................... 45

BCLK Signal Integrity Waveform ................................................................................................ 48

Low-to-High FSB Receiver Ringback Tolerance ........................................................................ 49

High-to-Low FSB Receiver Ringback Tolerance ........................................................................ 49

Low-to-High FSB Receiver Ringback Tolerance for PWRGOOD and TAP Buffers ................... 50

High-to-Low FSB Receiver Ringback Tolerance for PWRGOOD and TAP Buffers ................... 50

Maximum Acceptable Overshoot/Undershoot Waveform........................................................... 56

Micro-FCPGA Package Top and Bottom Isometric Views.......................................................... 57

Micro-FCPGA Package - Top and Side Views ........................................................................... 58

Micro-FCPGA Package - Bottom View ....................................................................................... 60

The Coordinates of the Processor Pins as Viewed From the Top of the Package..................... 61

Clock Control States ................................................................................................................... 90

Mobile Intel

Celeron

Processor on .13 Micron Process

and in Micro-FCPGA Package Datasheet

RH80532NC021256 Related Products

	RH80532NC021256	RH80532NC033256
Description	Microprocessor, 32-Bit, 1500MHz, CMOS, CPGA478, MICRO, FLIP CHIP, PGA-478	Microprocessor, 32-Bit, 1800MHz, CMOS, CPGA478, MICRO, FLIP CHIP, PGA-478
Is it Rohs certified?	conform to	conform to
Parts packaging code	PGA	PGA
package instruction	SPGA, PGA478,26X26,50	SPGA, PGA478,26X26,50
Contacts	478	478
Reach Compliance Code	unknown	unknown
ECCN code	3A001.A.3	3A001.A.3
Address bus width	36	36
bit size	32	32
boundary scan	YES	YES
maximum clock frequency	100 MHz	100 MHz
External data bus width	64	64
Format	FLOATING POINT	FLOATING POINT
Integrated cache	YES	YES
JESD-30 code	S-CPGA-P478	S-CPGA-P478
length	35 mm	35 mm
low power mode	YES	YES
Number of terminals	478	478
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	SPGA	SPGA
Encapsulate equivalent code	PGA478,26X26,50	PGA478,26X26,50
Package shape	SQUARE	SQUARE
Package form	GRID ARRAY, SHRINK PITCH	GRID ARRAY, SHRINK PITCH
power supply	1.3 V	1.3 V
Certification status	Not Qualified	Not Qualified
Maximum seat height	3.28 mm	3.28 mm
speed	1500 MHz	1800 MHz
Maximum slew rate	27500 mA	31000 mA
Nominal supply voltage	1.3 V	1.3 V
surface mount	NO	NO
technology	CMOS	CMOS
Terminal form	PIN/PEG	PIN/PEG
Terminal pitch	1.27 mm	1.27 mm
Terminal location	PERPENDICULAR	PERPENDICULAR
width	35 mm	35 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR	MICROPROCESSOR
Base Number Matches	1	1

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