Mobile Intel
Celeron
Processor
on .13 Micron Process and in
Micro-FCPGA Package
Datasheet
November 2003
Order Number: 251308-006
Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any
patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Information
contained herein supersedes previously published specifications on these devices from Intel.
Actual system-level properties, such as skin temperature, are a function of various factors, including component placement, component power
characteristics, system power and thermal management techniques, software application usage and general system design. Intel is not responsible
for its customers' system designs, nor is Intel responsible for ensuring that its customers' products comply with all applicable laws and regulations.
Intel provides this and other thermal design information for informational purposes only. System design is the sole responsibility of Intel's customers,
and Intel's customers should not rely on any Intel-provided information as either an endorsement or recommendation of any particular system design
characteristics.
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The mobile Intel Celeron processor may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-
548-4725 or by visiting Intel’s website at http://www.intel.com
Copyright © 2002-2003 Intel Corporation.
Intel, Celeron, and Intel NetBurst are registered trademarks or trademarks of Intel Corporation and its subsidiares in the United States and other
countries.
* Other brands and names may be claimed as property of others.
2
Mobile Intel
®
Celeron
®
Processor on .13 Micron Process
and in Micro-FCPGA Package Datasheet
Contents
1
Introduction...................................................................................................................................... 9
1.1
1.2
2
2.1
2.2
2.3
Terminology ........................................................................................................................ 10
References ......................................................................................................................... 10
FSB and GTLREF............................................................................................................... 11
Power and Ground Pins...................................................................................................... 11
Decoupling Guidelines........................................................................................................ 11
2.3.1 VCC Decoupling .................................................................................................... 12
2.3.2 FSB AGTL+ Decoupling ........................................................................................ 12
2.3.3 FSB Clock (BCLK[1:0]) and Processor Clocking ................................................... 12
Voltage Identification and Power Sequencing .................................................................... 13
2.4.1 Phase Lock Loop (PLL) Power and Filter .............................................................. 14
2.4.2 Catastrophic Thermal Protection ........................................................................... 16
Signal Terminations, Unused Pins and TESTHI[11:0] ........................................................ 16
FSB Signal Groups ............................................................................................................. 18
Asynchronous GTL+ Signals ..............................................................................................20
Test Access Port (TAP) Connection ................................................................................... 20
FSB Frequency Select Signals (BSEL[1:0]) ....................................................................... 20
Maximum Ratings ............................................................................................................... 21
Processor DC Specifications ..............................................................................................21
AGTL+ FSB Specifications ................................................................................................. 30
FSB AC Specifications........................................................................................................ 31
Processor AC Timing Waveforms....................................................................................... 36
FSB Clock (BCLK) Signal Quality Specifications and Measurement Guidelines................ 47
FSB Signal Quality Specifications and Measurement Guidelines ...................................... 48
FSB Signal Quality Specifications and Measurement Guidelines ...................................... 51
3.3.1 Overshoot/Undershoot Guidelines......................................................................... 51
3.3.2 Overshoot/Undershoot Magnitude ......................................................................... 51
3.3.3 Overshoot/Undershoot Pulse Duration .................................................................. 51
3.3.4 Activity Factor ........................................................................................................ 52
3.3.5 Reading Overshoot/Undershoot Specification Tables ........................................... 52
3.3.6 Conformance Determination to Overshoot/Undershoot Specifications.................. 53
Processor Pin-Out .............................................................................................................. 60
Mobile Intel Celeron Processor Pin Assignments ............................................................... 63
Alphabetical Signals Reference .......................................................................................... 79
Thermal Specifications ....................................................................................................... 88
6.1.1 Thermal Diode ....................................................................................................... 88
6.1.2 Thermal Monitor..................................................................................................... 89
Electrical Specifications ................................................................................................................. 11
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
3
3.1
3.2
3.3
FSB Signal Quality Specifications ................................................................................................. 47
4
5
Package Mechanical Specifications ..............................................................................................57
4.1
5.1
5.2
Pin Listing and Signal Definitions .................................................................................................. 63
6
Thermal Specifications and Design Considerations ...................................................................... 87
6.1
Mobile Intel
®
Celeron
®
Processor on .13 Micron Process
and in Micro-FCPGA Package Datasheet
3
7
Configuration and Low Power Features ........................................................................................ 91
7.1
7.2
Power-On Configuration Options........................................................................................ 91
Clock Control and Low Power States ................................................................................. 91
7.2.1 Normal State.......................................................................................................... 91
7.2.2 AutoHALT Powerdown State ................................................................................. 92
7.2.3 Stop-Grant State.................................................................................................... 92
7.2.4 HALT/Grant Snoop State....................................................................................... 93
7.2.5 Sleep State ............................................................................................................ 93
7.2.6 Deep Sleep State................................................................................................... 94
Logic Analyzer Interface (LAI) ............................................................................................ 95
8.1.1 Mechanical Considerations.................................................................................... 95
8.1.2 Electrical Considerations ....................................................................................... 95
8
Debug Tools Specifications ........................................................................................................... 95
8.1
4
Mobile Intel
®
Celeron
®
Processor on .13 Micron Process
and in Micro-FCPGA Package Datasheet
Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
VCCVID Pin Voltage and Current Requirements ....................................................................... 13
Typical VCCIOPLL, VCCA and VSSA Power Distribution.......................................................... 15
Phase Lock Loop (PLL) Filter Requirements............................................................................. 16
Illustration of VCC Static and Transient Tolerances (VID = 1.30 V) ........................................... 24
Illustration of Deep Sleep VCC Static and Transient Tolerances (VID Setting = 1.30 V) ........... 25
ITPCLKOUT[1:0] Output Buffer Diagram.................................................................................... 30
AC Test Circuit............................................................................................................................ 37
TCK Clock Waveform ................................................................................................................. 37
Differential Clock Waveform ....................................................................................................... 38
Differential Clock Crosspoint Specification ................................................................................. 39
FSB Common Clock Valid Delay Timings .................................................................................. 39
FSB Reset and Configuration Timings ....................................................................................... 40
Source Synchronous 2X (Address) Timings............................................................................... 40
Source Synchronous 4X Timings ............................................................................................... 41
Power Up Sequence.................................................................................................................. 42
Power Down Sequence .............................................................................................................. 42
Test Reset Timings..................................................................................................................... 43
THERMTRIP# to Vcc Timing ...................................................................................................... 43
FERR#/PBE# Valid Delay Timing............................................................................................... 43
TAP Valid Delay Timing.............................................................................................................. 44
ITPCLKOUT Valid Delay Timing.................................................................................................44
Stop Grant/Sleep/Deep Sleep Timing......................................................................................... 45
BCLK Signal Integrity Waveform ................................................................................................ 48
Low-to-High FSB Receiver Ringback Tolerance ........................................................................ 49
High-to-Low FSB Receiver Ringback Tolerance ........................................................................ 49
Low-to-High FSB Receiver Ringback Tolerance for PWRGOOD and TAP Buffers ................... 50
High-to-Low FSB Receiver Ringback Tolerance for PWRGOOD and TAP Buffers ................... 50
Maximum Acceptable Overshoot/Undershoot Waveform........................................................... 56
Micro-FCPGA Package Top and Bottom Isometric Views.......................................................... 57
Micro-FCPGA Package - Top and Side Views ........................................................................... 58
Micro-FCPGA Package - Bottom View ....................................................................................... 60
The Coordinates of the Processor Pins as Viewed From the Top of the Package..................... 61
Clock Control States ................................................................................................................... 90
Mobile Intel
®
Celeron
®
Processor on .13 Micron Process
and in Micro-FCPGA Package Datasheet
5
京公网安备 11010802033920号
EEWORLD
