Mobile Intel
Pentium
4
Processor-M
Datasheet
September 2002
Order Number: 250686-004
Mobile Intel
Pentium
4 Processor-M
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for such products. Information contained herein supersedes previously published specifications on these devices from Intel.
Actual system-level properties, such as skin temperature, are a function of various factors, including component placement,
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Datasheet
250686-004
Mobile Intel
Pentium
4 Processor-M
Contents
1.
Introduction......................................................................................................................... 9
1.1
1.2
2.
2.1
2.2
2.3
Terminology.........................................................................................................10
1.1.1 Terminology............................................................................................10
References ..........................................................................................................11
System Bus and GTLREF ...................................................................................13
Power and Ground Pins ......................................................................................13
Decoupling Guidelines ........................................................................................13
2.3.1 VCC Decoupling .....................................................................................14
2.3.2 System Bus AGTL+ Decoupling.............................................................14
2.3.3 System Bus Clock (BCLK[1:0]) and Processor Clocking .......................14
Voltage Identification and Power Sequencing.....................................................15
2.4.1 Enhanced Intel SpeedStep Technology .................................................16
2.4.2 Phase Lock Loop (PLL) Power and Filter...............................................17
2.4.3 Catastrophic Thermal Protection............................................................18
Signal Terminations, Unused Pins and TESTHI[10:0] ........................................18
System Bus Signal Groups .................................................................................20
Asynchronous GTL+ Signals...............................................................................22
Test Access Port (TAP) Connection....................................................................22
System Bus Frequency Select Signals (BSEL[1:0])............................................22
Maximum Ratings................................................................................................23
Processor DC Specifications...............................................................................23
AGTL+ System Bus Specifications .....................................................................34
System Bus AC Specifications ............................................................................35
Processor AC Timing Waveforms .......................................................................40
System Bus Clock (BCLK) Signal Quality Specifications and Measurement
Guidelines ...........................................................................................................51
System Bus Signal Quality Specifications and Measurement Guidelines...........52
System Bus Signal Quality Specifications and Measurement Guidelines...........55
3.3.1 Overshoot/Undershoot Guidelines .........................................................55
3.3.2 Overshoot/Undershoot Magnitude .........................................................55
3.3.3 Overshoot/Undershoot Pulse Duration...................................................55
3.3.4 Activity Factor .........................................................................................56
3.3.5 Reading Overshoot/Undershoot Specification Tables............................56
3.3.6 Conformance Determination to Overshoot/Undershoot Specifications ..57
Processor Pin-Out ...............................................................................................64
Mobile Intel Pentium 4 Processor-M Pin Assignments........................................67
Alphabetical Signals Reference ..........................................................................81
Electrical Specifications....................................................................................................13
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
3.
3.1
3.2
3.3
System Bus Signal Quality Specifications........................................................................51
4.
5.
Package Mechanical Specifications .................................................................................61
4.1
5.1
5.2
Pin Listing and Signal Definitions .....................................................................................67
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Datasheet
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Mobile Intel
Pentium
4 Processor-M
6.
Thermal Specifications and Design Considerations......................................................... 89
6.1
Thermal Specifications........................................................................................ 90
6.1.1 Thermal Diode........................................................................................ 90
6.1.2 Thermal Monitor ..................................................................................... 91
Power-On Configuration Options ........................................................................ 93
Clock Control and Low Power States.................................................................. 93
7.2.1 Normal State .......................................................................................... 93
7.2.2 AutoHALT Powerdown State ................................................................. 93
7.2.3 Stop-Grant State .................................................................................... 94
7.2.4 HALT/Grant Snoop State ....................................................................... 95
7.2.5 Sleep State............................................................................................. 95
7.2.6 Deep Sleep State ................................................................................... 95
7.2.7 Deeper Sleep State................................................................................ 96
Enhanced Intel SpeedStep Technology.............................................................. 96
Logic Analyzer Interface (LAI)............................................................................ 97
8.1.1 Mechanical Considerations .................................................................... 97
8.1.2 Electrical Considerations........................................................................ 97
7.
Configuration and Low Power Features........................................................................... 93
7.1
7.2
7.3
8.
8.1
Debug Tools Specifications.............................................................................................. 97
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Datasheet
250686-004
Mobile Intel
Pentium
4 Processor-M
Figures
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VCCVID Pin Voltage and Current Requirements ................................................15
Typical VCCIOPLL, VCCA and VSSA Power Distribution ..................................17
Phase Lock Loop (PLL) Filter Requirements .....................................................18
Illustration of VCC Static and Transient Tolerances (VID = 1.30 V)....................26
Illustration of VCC Static and Transient Tolerances (VID = 1.20 V)....................28
Illustration of Deep Sleep VCC Static and Transient Tolerances (VID Setting =
1.30 V).................................................................................................................29
ITPCLKOUT[1:0] Output Buffer Diagram ............................................................34
AC Test Circuit ....................................................................................................41
TCK Clock Waveform..........................................................................................41
Differential Clock Waveform................................................................................42
Differential Clock Crosspoint Specification..........................................................43
System Bus Common Clock Valid Delay Timings...............................................43
System Bus Reset and Configuration Timings....................................................44
Source Synchronous 2X (Address) Timings .......................................................44
Source Synchronous 4X Timings ........................................................................45
Power Up Sequence ..........................................................................................46
Power Down Sequence.......................................................................................46
Test Reset Timings .............................................................................................47
THERMTRIP# to Vcc Timing...............................................................................47
FERR#/PBE# Valid Delay Timing .......................................................................47
TAP Valid Delay Timing ......................................................................................48
ITPCLKOUT Valid Delay Timing .........................................................................48
Stop Grant/Sleep/Deep Sleep Timing .................................................................49
Enhanced Intel SpeedStep Technology/Deep Sleep Timing ..............................50
BCLK Signal Integrity Waveform.........................................................................52
Low-to-High System Bus Receiver Ringback Tolerance.....................................53
High-to-Low System Bus Receiver Ringback Tolerance.....................................53
Low-to-High System Bus Receiver Ringback Tolerance for PWRGOOD and
TAP Buffers .........................................................................................................54
High-to-Low System Bus Receiver Ringback Tolerance for PWRGOOD and
TAP Buffers .........................................................................................................54
Maximum Acceptable Overshoot/Undershoot Waveform ...................................59
Micro-FCPGA Package Top and Bottom Isometric Views ..................................61
Micro-FCPGA Package Top and Side View........................................................62
Micro-FCPGA Package - Bottom View................................................................64
The Coordinates of the Processor Pins as Viewed From the Top of the
Package. .............................................................................................................65
Clock Control States............................................................................................94
250686-004
Datasheet
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