RH8053GC033512 datasheet, PDF - EEWORLD Datasheet

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RH8053GC033512: DescriptionRISC Microprocessor, 64-Bit, CMOS, PPGA478; CategoryThe embedded processor and controller Microcontrollers and processors; File Size4MB，97 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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RH8053GC033512 Overview

RISC Microprocessor, 64-Bit, CMOS, PPGA478

RH8053GC033512 Parametric

Parameter Name	Attribute value
package instruction	SPGA, PGA478,26X26,50
Reach Compliance Code	compliant
bit size	64
JESD-30 code	S-PPGA-P478
Number of terminals	478
Package body material	PLASTIC/EPOXY
encapsulated code	SPGA
Encapsulate equivalent code	PGA478,26X26,50
Package shape	SQUARE
Package form	GRID ARRAY, SHRINK PITCH
power supply	1.2 V
Certification status	Not Qualified
Nominal supply voltage	1.2 V
surface mount	NO
technology	CMOS
Terminal form	PIN/PEG
Terminal pitch	1.27 mm
Terminal location	PERPENDICULAR
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC
Base Number Matches	1

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Mobile Intel



Pentium



Processor-M

Datasheet

September 2002

Order Number: 250686-004

Mobile Intel



Pentium



4 Processor-M

Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including

infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale

for such products. Information contained herein supersedes previously published specifications on these devices from Intel.

Actual system-level properties, such as skin temperature, are a function of various factors, including component placement,

component power characteristics, system power and thermal management techniques, software application usage and general

system design. Intel is not responsible for its customers' system designs, nor is Intel responsible for ensuring that its customers'

products comply with all applicable laws and regulations. Intel provides this and other thermal design information for informational

purposes only. System design is the sole responsibility of Intel's customers, and Intel's customers should not rely on any Intel-

provided information as either an endorsement or recommendation of any particular system design characteristics.

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise,

to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such

products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of

Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any

patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining

applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel

reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future

changes to them.

The Mobile Intel Pentium 4 Processor-M may contain design defects or errors known as errata which may cause the product to

deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be

obtained by calling 1-800-548-4725 or by visiting Intel’s Website at http://www.intel.com

Intel, Pentium, Intel NetBurst, and SpeedStep are registered trademarks or trademarks of Intel Corporation and its subsidiaries in

the United States and other countries.

* Other brands and names are the property of their respective owners.

Datasheet

250686-004

Mobile Intel



Pentium



4 Processor-M

Contents

Introduction......................................................................................................................... 9

1.1

1.2

2.1

2.2

2.3

Terminology.........................................................................................................10

1.1.1 Terminology............................................................................................10

References ..........................................................................................................11

System Bus and GTLREF ...................................................................................13

Power and Ground Pins ......................................................................................13

Decoupling Guidelines ........................................................................................13

2.3.1 VCC Decoupling .....................................................................................14

2.3.2 System Bus AGTL+ Decoupling.............................................................14

2.3.3 System Bus Clock (BCLK[1:0]) and Processor Clocking .......................14

Voltage Identification and Power Sequencing.....................................................15

2.4.1 Enhanced Intel SpeedStep Technology .................................................16

2.4.2 Phase Lock Loop (PLL) Power and Filter...............................................17

2.4.3 Catastrophic Thermal Protection............................................................18

Signal Terminations, Unused Pins and TESTHI[10:0] ........................................18

System Bus Signal Groups .................................................................................20

Asynchronous GTL+ Signals...............................................................................22

Test Access Port (TAP) Connection....................................................................22

System Bus Frequency Select Signals (BSEL[1:0])............................................22

Maximum Ratings................................................................................................23

Processor DC Specifications...............................................................................23

AGTL+ System Bus Specifications .....................................................................34

System Bus AC Specifications ............................................................................35

Processor AC Timing Waveforms .......................................................................40

System Bus Clock (BCLK) Signal Quality Specifications and Measurement

Guidelines ...........................................................................................................51

System Bus Signal Quality Specifications and Measurement Guidelines...........52

System Bus Signal Quality Specifications and Measurement Guidelines...........55

3.3.1 Overshoot/Undershoot Guidelines .........................................................55

3.3.2 Overshoot/Undershoot Magnitude .........................................................55

3.3.3 Overshoot/Undershoot Pulse Duration...................................................55

3.3.4 Activity Factor .........................................................................................56

3.3.5 Reading Overshoot/Undershoot Specification Tables............................56

3.3.6 Conformance Determination to Overshoot/Undershoot Specifications ..57

Processor Pin-Out ...............................................................................................64

Mobile Intel Pentium 4 Processor-M Pin Assignments........................................67

Alphabetical Signals Reference ..........................................................................81

Electrical Specifications....................................................................................................13

2.4

2.5

2.6

2.7

2.8

2.9

2.10

2.11

2.12

2.13

2.14

3.1

3.2

3.3

System Bus Signal Quality Specifications........................................................................51

Package Mechanical Specifications .................................................................................61

4.1

5.1

5.2

Pin Listing and Signal Definitions .....................................................................................67

250686-004

Datasheet

Mobile Intel



Pentium



4 Processor-M

Thermal Specifications and Design Considerations......................................................... 89

6.1

Thermal Specifications........................................................................................ 90

6.1.1 Thermal Diode........................................................................................ 90

6.1.2 Thermal Monitor ..................................................................................... 91

Power-On Configuration Options ........................................................................ 93

Clock Control and Low Power States.................................................................. 93

7.2.1 Normal State .......................................................................................... 93

7.2.2 AutoHALT Powerdown State ................................................................. 93

7.2.3 Stop-Grant State .................................................................................... 94

7.2.4 HALT/Grant Snoop State ....................................................................... 95

7.2.5 Sleep State............................................................................................. 95

7.2.6 Deep Sleep State ................................................................................... 95

7.2.7 Deeper Sleep State................................................................................ 96

Enhanced Intel SpeedStep Technology.............................................................. 96

Logic Analyzer Interface (LAI)............................................................................ 97

8.1.1 Mechanical Considerations .................................................................... 97

8.1.2 Electrical Considerations........................................................................ 97

Configuration and Low Power Features........................................................................... 93

7.1

7.2

7.3

8.1

Debug Tools Specifications.............................................................................................. 97

Datasheet

250686-004

Mobile Intel



Pentium



4 Processor-M

Figures

VCCVID Pin Voltage and Current Requirements ................................................15

Typical VCCIOPLL, VCCA and VSSA Power Distribution ..................................17

Phase Lock Loop (PLL) Filter Requirements .....................................................18

Illustration of VCC Static and Transient Tolerances (VID = 1.30 V)....................26

Illustration of VCC Static and Transient Tolerances (VID = 1.20 V)....................28

Illustration of Deep Sleep VCC Static and Transient Tolerances (VID Setting =

1.30 V).................................................................................................................29

ITPCLKOUT[1:0] Output Buffer Diagram ............................................................34

AC Test Circuit ....................................................................................................41

TCK Clock Waveform..........................................................................................41

Differential Clock Waveform................................................................................42

Differential Clock Crosspoint Specification..........................................................43

System Bus Common Clock Valid Delay Timings...............................................43

System Bus Reset and Configuration Timings....................................................44

Source Synchronous 2X (Address) Timings .......................................................44

Source Synchronous 4X Timings ........................................................................45

Power Up Sequence ..........................................................................................46

Power Down Sequence.......................................................................................46

Test Reset Timings .............................................................................................47

THERMTRIP# to Vcc Timing...............................................................................47

FERR#/PBE# Valid Delay Timing .......................................................................47

TAP Valid Delay Timing ......................................................................................48

ITPCLKOUT Valid Delay Timing .........................................................................48

Stop Grant/Sleep/Deep Sleep Timing .................................................................49

Enhanced Intel SpeedStep Technology/Deep Sleep Timing ..............................50

BCLK Signal Integrity Waveform.........................................................................52

Low-to-High System Bus Receiver Ringback Tolerance.....................................53

High-to-Low System Bus Receiver Ringback Tolerance.....................................53

Low-to-High System Bus Receiver Ringback Tolerance for PWRGOOD and

TAP Buffers .........................................................................................................54

High-to-Low System Bus Receiver Ringback Tolerance for PWRGOOD and

TAP Buffers .........................................................................................................54

Maximum Acceptable Overshoot/Undershoot Waveform ...................................59

Micro-FCPGA Package Top and Bottom Isometric Views ..................................61

Micro-FCPGA Package Top and Side View........................................................62

Micro-FCPGA Package - Bottom View................................................................64

The Coordinates of the Processor Pins as Viewed From the Top of the

Package. .............................................................................................................65

Clock Control States............................................................................................94

250686-004

Datasheet

RH8053GC033512 Related Products

	RH8053GC033512	RH8053GC017512	RH8053GC021512	RH8053GC025512
Description	RISC Microprocessor, 64-Bit, CMOS, PPGA478	RISC Microprocessor, 64-Bit, CMOS, PPGA478	RISC Microprocessor, 64-Bit, CMOS, PPGA478	RISC Microprocessor, 64-Bit, CMOS, PPGA478
package instruction	SPGA, PGA478,26X26,50	SPGA, PGA478,26X26,50	SPGA, PGA478,26X26,50	SPGA, PGA478,26X26,50
Reach Compliance Code	compliant	compliant	compliant	compliant
bit size	64	64	64	64
JESD-30 code	S-PPGA-P478	S-PPGA-P478	S-PPGA-P478	S-PPGA-P478
Number of terminals	478	478	478	478
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SPGA	SPGA	SPGA	SPGA
Encapsulate equivalent code	PGA478,26X26,50	PGA478,26X26,50	PGA478,26X26,50	PGA478,26X26,50
Package shape	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY, SHRINK PITCH	GRID ARRAY, SHRINK PITCH	GRID ARRAY, SHRINK PITCH	GRID ARRAY, SHRINK PITCH
power supply	1.2 V	1.2 V	1.2 V	1.2 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Nominal supply voltage	1.2 V	1.2 V	1.2 V	1.2 V
surface mount	NO	NO	NO	NO
technology	CMOS	CMOS	CMOS	CMOS
Terminal form	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC
Base Number Matches	1	1	1	1

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