DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD78P048A
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The
µ
PD78P048A is a product in the
µ
PD78044F subseries within the 78K/0 series, in which the internal ROM
of the
µ
PD78042F, 78043F, 78044F, and 78045F is replaced with one-time PROM or EPROM.
As the
µ
PD78P048A is user-programmable, it is ideal for evaluation in system development, short-run and multiple-
device production, and early start-up.
Details of functions are described in the User's Manuals shown below. Be sure to read in design.
µ
PD78044F subseries User's Manual: U10908E
78K/0 series User's Manual -Instruction: U12326E
FEATURES
•
•
•
•
•
•
•
Pin compatible with mask ROM products (except the V
PP
pin)
Internal PROM: 60K bytes
Note 1
Internal high-speed RAM: 1024 bytes
Note 1
Internal expansion RAM: 1024 bytes
Note 2
Buffer RAM: 64 bytes
FIP
TM
display RAM: 48 bytes
Operable in the same supply voltage as mask ROM products: V
DD
= 2.7 to 6.0 V (except A/D converter)
A/D converter supply voltage: AV
DD
= 4.0 to 6.0
Notes 1.
2.
Internal PROM and internal high-speed RAM capacities can be changed by memory size switch-
ing register (IMS).
Internal expansion RAM capacity can be changed by internal expansion RAM size switching
register (IXS).
Remark
For the difference between ROM products and mask ROM products, refer to
1. DIFFERENCES
BETWEEN
µ
PD78P048A AND MASK ROM PRODUCTS.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. U10611EJ2V1DS00 (2nd edition)
Date Published August 2005 N CP(K)
Printed in Japan
The mark
shows major revised points.
1993
µ
PD78P048A
ORDERING INFORMATION
Part Number
Package
80-pin plastic QFP (14 x 20)
80-pin plastic QFP (14 x 20)
Internal ROM
One-time PROM
One-time PROM
µ
PD78P048AGF-3B9
µ
PD78P048AGF-3B9-A
Remark
Products that have the part numbers suffixed by “-A” are lead-free products.
2
Data Sheet U10611EJ2V1DS
µ
PD78P048A
78K/0 SERIES PRODUCT DEVELOPMENT
The following shows the 78K/0 Series products development. Subseries name are shown inside frames.
Control
100-pin
100-pin
100-pin
100-pin
80-pin
80-pin
80-pin
64-pin
64-pin
64-pin
64-pin
64-pin
64-pin
64-pin
42/44-pin
Products in
mass production
Products under
development
Y subseries products are compatible with I
2
C bus.
EMI-noise reduced version of the
µ
PD78078
A timer was added to the
µ
PD78054 and external interface was enhanced
ROM-less version of the
µ
PD78078
Serial I/O of the
µ
PD78078 was enhanched and the function is limited
Serial I/O of the
µ
PD78054 was enhanced and EMI-noise was reduced
EMI-noise reduced version of the
µ
PD78054
UART and D/A converter were added to the
µ
PD78014 and I/O was enchanced
A/D converter of the
µ
PD780024 was enchanced
Serial I/O of the
µ
PD78018F was added and EMI-noise was reduced
EMI-noise reduced version of
µ
PD78018F
Low-voltage (1.8 V) operation version of the
µ
PD78014, with larger
selection of ROM and RAM capacities
An A/D converter and 16-bit timer were added to the
µ
PD78002
An A/D converter was added to the
µ
PD78002
Basic subseries for control
On-chip UART, capable of operating at low voltage (1.8 V)
µ
PD78075B
µ
PD78075BY
µ
PD78078
µ
PD78078Y
µ
PD78070A
µ
PD78070AY
Note
µ
PD780018
µ
PD780018Y
Note
µ
PD780058
µ
PD780058Y
Note
µ
PD78058F
µ
PD78058FY
µ
PD78054
µ
PD78054Y
µ
PD780034
µ
PD780034Y
µ
PD780024
µ
PD780024Y
µ
PD78014H
µ
PD78018F
µ
PD78018FY
µ
PD78014
µ
PD78014Y
µ
PD780001
µ
PD78002
µ
PD78002Y
µ
PD78083
Inverter control
64-pin
64-pin
78K/0
Series
µ
PD780964
µ
PD780924
FIP drive
A/D converter of the
µ
PD780924 was enhanced
On-chip inverter control circuit and UART. EMI-noise was reduced.
The I/O and FIP C/D of the
µ
PD78044F were enhanced, Display output total: 53
The I/O and FIP C/D of the
µ
PD78044H were enhanced, Display output total: 48
N-ch open drain was added to the
µ
PD78044F, Display output total: 34
Basic subseries for driving FIP, Display output total: 34
100-pin
100-pin
80-pin
80-pin
µ
PD780208
µ
PD780228
µ
PD78044H
µ
PD78044F
LCD drive
100-pin
100-pin
100-pin
µ
PD780308
µ
PD78064B
µ
PD78064
µ
PD780308Y
µ
PD78064Y
The SIO of the
µ
PD78064 was enhanced and ROM, RAM capacity increased
EMI-noise reduced version of the
µ
PD78064
Basic subseries for driving LCDs, On-chip UART
IEBus
TM
supported
80-pin
80-pin
µ
PD78098B
µ
PD78098
Meter control
EMI-noise reduced version of the
µ
PD78098
An IEBus controller was added to the
µ
PD78054
80-pin
100-pin
µ
PD780973
µ
PD780805
LV
General-purpose version of the
µ
PD780805 controller/driver for driving automobile meters
On-chip controller/driver for automobile meters
64-pin
µ
PD78P0914
On-chip PWM output, LV digital code decoder, and Hsync counter
Note
Under planning
Data Sheet U10611EJ2V1DS
3
µ
PD78P048A
The following lists the main functional differences between subseries products.
Function
Subseries Name
Control
ROM
Capacity
32 K-40 K
48 K-60 K
–
48 K-60 K
–
2 ch (time division
3-wire: 1ch)
3 ch (time division
UART: 1ch)
3 ch (UART: 1 ch)
61
88
2.7 V
Timer
8-bit
4 ch
16-bit Watch WDT
1 ch
1 ch
1 ch
8-bit
A/D
8 ch
10-bit 8-bit
A/D
D/A
–
2 ch
Serial
Interface
3 ch (UART : 1 ch)
V
DD
MIN. External
Value Expansion
1.8 V
I/O
µ
PD78075B
µ
PD78078
µ
PD78070A
µ
PD780018
µ
PD780058
µ
PD78058F
µ
PD78054
µ
PD780034
µ
PD780024
µ
PD78014H
µ
PD78018F
µ
PD78014
µ
PD780001
µ
PD78002
µ
PD78083
88
24 K-60 K
2 ch
2 ch
68
1.8 V
48 K-60 K
16 K-60 K
8 K-32 K
–
8 ch
8 ch
–
–
69
2.7 V
2.0 V
3 ch (UART: 1 ch, time
division 3-wire: 1 ch)
2 ch
51
1.8 V
53
8 K-60 K
8 K-32 K
8K
8 K-16 K
–
–
1 ch
–
8 K-32 K
3 ch
Note
–
1 ch
–
8 ch
–
8 ch
32 K-60 K
48 K-60 K
32 K-48 K
16 K-40 K
48 K-60 K
2 ch
1 ch
1 ch
1 ch
8 ch
–
–
2 ch
3 ch
2 ch
1 ch
–
1 ch
1 ch
–
1 ch
2 ch
3 ch (time division
UART: 1ch)
2 ch (UART : 1 ch)
57
2.0 V
–
1 ch
8 ch
8 ch
–
–
–
2 ch
1 ch
74
72
68
2.7 V
4.5 V
2.7 V
–
–
1 ch (UART: 1 ch)
2 ch (UART: 2 ch)
1 ch
39
53
33
47
1.8 V
2.7 V
–
2.7 V
–
Inverter
control
FIP
drive
µ
PD780964
µ
PD780924
µ
PD780208
µ
PD780228
µ
PD78044H
µ
PD78044F
LCD
drive
µ
PD780308
µ
PD78064B
µ
PD78064
32 K
16 K-32 K
40 K-60 K
32 K-60 K
24 K-32 K
40 K-60 K
32 K
3 ch
2 ch
6 ch
–
–
1 ch
1 ch
1 ch
1 ch
5 ch
8 ch
8 ch
–
–
–
–
2 ch
1 ch
1 ch
1 ch
8 ch
–
2 ch
IEBus
supported
Meter
control
LV
µ
PD78098B
µ
PD78098
µ
PD780973
µ
PD780805
µ
PD78P0914
3 ch (UART : 1 ch)
69
2.7 V
2 ch (UART : 1 ch)
56
39
4.5 V
2.7 V
4.5 V
–
2 ch
54
Note
10-bit timer: 1 channel
4
Data Sheet U10611EJ2V1DS
µ
PD78P048A
FUNCTION DESCRIPTION
Item
Internal
memory
PROM
High-speed RAM
Expansion RAM
Buffer RAM
FIP display RAM
General-purpose register
Minimum instruction execution time
When main system clock is selected
When subsystem clock is selected
Instruction set
60 K bytes
Note 1
1024 bytes
Note 1
1024 bytes
Note 2
64 bytes
48 bytes
8 bits
×
32 registers (8 bits
×
8 registers
×
4 banks)
Instruction execution time variable function is built in.
0.4
µ
s/0.8
µ
s/1.6
µ
s/3.2
µ
s/6.4
µ
s (when operating at 5.0 MHz)
122
µ
s (when operating at 32.768 kHz)
• Multiplication/division (8 bits
×
8 bits, 16 bits
÷
8 bits)
• Bit manipulation (set, reset, test, boolean operation)
Total
• CMOS input
• CMOS input/output
• N-ch open-drain input/output
• P-ch open-drain input/output
• P-ch open-drain output
FIP controller/driver
Display output total
• No. of segments
• No. of digits
: 34
: 9 to 24
: 2 to 16
: 68
: 2
: 27
: 5
: 16
: 18
Function
I/O ports
(including FIP dual-function pin)
A/D converter
• 8-bit resolution
×
8 ch
• Supply voltage: AV
DD
= 4.0 to 6.0 V
• 3-wire serial I/O/SBI/2-wire serial I/O mode selectable
: 1 ch
Serial interface
• 3-wire serial I/O mode (on-chip max. 64 bytes automatic data transmit/receive function): 1 ch
Timer
• 16-bit timer/event counter : 1 channel
• 8-bit timer/event counter : 2 channels
• Clock timer
• Watchdog timer
• 6-bit up/down counter
Timer output
Clock output
: 1 channel
: 1 channel
: 1 channel
3 (14-bit PWM output capability : 1)
19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz
(When operating at main system clock 5.0 MHz)
32.768 kHz (when operating at subsystem clock 32.768 kHz)
Buzzer output
Vectored
interrupt
sources
Software
Test input
Supply voltage
Package
Maskable
Non-maskable
1.2 kHz, 2.4 kHz, 4.9 kHz (when operating at main system clock 5.0 MHz)
Internal: 10, External: 4
Internal: 1
1
Internal: 1
V
DD
= 2.7 to 6.0 V
80-pin plastic QFP (14 x 20)
Notes 1.
Internal PROM/internal high-speed RAM capacity can be changed by memory size switching register (IMS).
2.
Internal expansion RAM capacity can be changed by internal expansion RAM size switching register (IXS).
Data Sheet U10611EJ2V1DS
5
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