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IDT70V631S10BF8

Description
Dual-Port SRAM, 256KX18, 10ns, CMOS, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, FPBGA-208
Categorystorage    storage   
File Size183KB,23 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

IDT70V631S10BF8 Overview

Dual-Port SRAM, 256KX18, 10ns, CMOS, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, FPBGA-208

IDT70V631S10BF8 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
Parts packaging codeBGA
package instructionLFBGA, BGA208,17X17,32
Contacts208
Reach Compliance Codenot_compliant
ECCN code3A991.B.2.A
Maximum access time10 ns
I/O typeCOMMON
JESD-30 codeS-PBGA-B208
JESD-609 codee0
length15 mm
memory density4718592 bit
Memory IC TypeDUAL-PORT SRAM
memory width18
Humidity sensitivity level3
Number of functions1
Number of ports2
Number of terminals208
word count262144 words
character code256000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize256KX18
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeLFBGA
Encapsulate equivalent codeBGA208,17X17,32
Package shapeSQUARE
Package formGRID ARRAY, LOW PROFILE, FINE PITCH
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)225
power supply2.5/3.3,3.3 V
Certification statusNot Qualified
Maximum seat height1.7 mm
Maximum standby current0.015 A
Minimum standby current3.15 V
Maximum slew rate0.5 mA
Maximum supply voltage (Vsup)3.45 V
Minimum supply voltage (Vsup)3.15 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn63Pb37)
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature20
width15 mm
Base Number Matches1
HIGH-SPEED 3.3V 256K x 18
ASYNCHRONOUS DUAL-PORT
STATIC RAM
x
PRELIMINARY
IDT70V631S
Features
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 10/12/15ns (max.)
– Industrial: 12/15ns (max.)
Dual chip enables allow for depth expansion without
external logic
IDT70V631 easily expands data bus width to 36 bits or
more using the Master/Slave select when cascading more
than one device
M/S = V
IH
for
BUSY
output flag on Master,
M/S = V
IL
for
BUSY
input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
UB
L
LB
L
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Fully asynchronous operation from either port
Separate byte controls for multiplexed bus and bus
matching compatibility
Supports JTAG features compliant to IEEE 1149.1
– Due to limited pin count, JTAG is not supported on the
128-pin TQFP package.
LVTTL-compatible, single 3.3V (±150mV) power supply for
core
LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)
power supply for I/Os and control signals on each port
Available in a 128-pin Thin Quad Flatpack, 208-ball fine
pitch Ball Grid Array, and 256-ball Ball Grid Array
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Functional Block Diagram
UB
R
LB
R
R/W
L
B
E
0
L
B
E
1
L
B
E
1
R
B
E
0
R
R/W
R
CE
0 L
CE
1 L
CE
0 R
CE
1 R
OE
L
Dout0-8_L
Dout9-17_L
Dout0-8_R
Dout9-17_R
OE
R
256K x 18
MEMORY
ARRAY
I/O
0L
- I/O
17L
Din_L
Din_R
I/O
0R
- I/O
17R
A
17L
A
0L
Address
Decoder
ADDR_L
ADDR_R
Address
Decoder
A
17R
A
0R
OE
L
CE
0L
CE
1L
R/W
L
BUSY
L
SEM
L
INT
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
OE
R
CE
0 R
CE
1 R
R/W
R
BUSY
R
M/S
SEM
R
INT
R
TDI
TDO
JTAG
TMS
TCK
TRST
5622 drw 01
NOTES:
1.
BUSY
is an input as a Slave (M/S=V
IL
) and an output when it is a Master (M/S=V
IH
).
2.
BUSY
and
INT
are non-tri-state totem-pole outputs (push-pull).
AUGUST 2001
DSC-5622/4
1
©2001 Integrated Device Technology, Inc.
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