M2732A
NMOS 32K (4K x 8) UV EPROM
FAST ACCESS TIME: 200ns
EXTENDED TEMPERATURE RANGE
SINGLE 5V SUPPLY VOLTAGE
LOW STANDBY CURRENT: 35mA max
INPUTS and OUTPUTS TTL COMPATIBLE
DURING READ and PROGRAM
COMPLETELY STATIC
24
1
FDIP24W (F)
DESCRIPTION
The M2732A is a 32,768 bit UV erasable and
electrically programmable memory EPROM. It is
organized as 4,096 words by 8 bits. The M2732A
with its single 5V power supply and with an access
time of 200 ns, is ideal suited for applications where
fast turn around and pattern experimentation one
important requirements.
The M2732A is honsed in a 24 pin Window Ceramic
Frit-Seal Dual-in-Line package. The transparent lid
allows the user to expose the chip to ultraviolet light
to erase the bit pattern. A new pattern can be then
written to the clerice by following the programming
procedure.
Figure 1. Logic Diagram
VCC
12
A0-A11
8
Q0-Q7
E
M2732A
Table 1. Signal Names
A0 - A11
Q0 - Q7
E
GV
PP
V
CC
V
SS
Address Inputs
Data Outputs
Chip Enable
Output Enable / Program Supply
Supply Voltage
Ground
GVPP
VSS
AI00780B
July 1994
1/9
M2732A
Table 2. Absolute Maximum Ratings
Symbol
T
A
T
BIAS
T
STG
V
IO
V
CC
V
PP
Parameter
Ambient Operating Temperature
Temperature Under Bias
Storage Temperature
Input or Output Voltages
Supply Voltage
Program Supply Voltage
grade 1
grade 6
grade 1
grade 6
Value
0 to 70
–40 to 85
–10 to 80
–50 to 95
–65 to 125
–0.6 to 6
–0.6 to 6
–0.6 to 22
Unit
°C
°C
°C
V
V
V
Note:
Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause
permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those
indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods
may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents.
Figure 2. DIP Pin Connections
be used to gate data to the output pins, inde-
pendent of device selection.
Assuming that the addresses are stable, address
access time (t
AVAQ
) is equal to the delay from E to
output (t
ELQV
). Data is available at the outputs after
the falling edge of G, assuming that E has been low
and the addresses have been stable for at least
t
AVQV
-t
GLQV
.
Standby Mode
The M2732A has a standby mode which reduces
the active power current by 70 %, from 125 mA to
35 mA. The M2732A is placed in the standby mode
by applying a TTL high signal to E input. When in
standby mode, the outputs are in a high impedance
state, independent of the GV
PP
input.
Two Line Output Control
Because M2732A’s are usually used in larger mem-
ory arrays, this product features a 2 line control
function which accommodates the use of multiple
memory connection. The two line control function
allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
To most efficiently use these two control lines, it is
recommended that E be decoded and used as the
primary device selecting function, while G should
be made a common connection to all devices in the
array and connected to the READ line from the
system control bus.
This ensures that all deselected memory devices
are in their low power standby mode and that the
output pins are only active when data is required
from a particular memory device.
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
VSS
24
1
2
23
3
22
4
21
20
5
6 M2732A 19
18
7
17
8
16
9
15
10
11
14
12
13
AI00781
VCC
A8
A9
A11
GVPP
A10
E
Q7
Q6
Q5
Q4
Q3
DEVICE OPERATION
The six modes of operation for the M2732A are
listed in the Operating Modes Table. A single 5V
power supply is required in the read mode. All
inputs are TTL level except for V
PP.
Read Mode
The M2732A has two control functions, both of
which must be logically satisfied in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
2/9
M2732A
Programming
When delivered, and after each erasure, all bits of
the M2732A are in the “1" state. Data is introduced
by selectively programming ”0’s" into the desired
bit locations. Although only “0’s” will be pro-
grammed, both “1’s” and “0’s” can be presented in
the data word. The only way to change a “0" to a
”1" is by ultraviolet light erasure.
The M2732A is in the programming mode when the
GV
PP
input is at 21V. A 0.1µF capacitor must be
placed across GV
PP
and ground to suppress spu-
rious voltage transients which may damage the
device. The data to be programmed is applied, 8
bits in parallel, to the data output pins. The levels
required for the address and data inputs are TTL.
When the address and data are stable, a 50ms,
active low, TTL program pulse is applied to the E
input. A program pulse must be applied at each
address location to be programmed. Any location
can be programmed at any time - either individually,
sequentially, or at random. The program pulse has
a maximum width of 55ms. The M2732A must not
be programmed with a DC signal applied to the E
input.
Programming of multiple M2732As in parallel with
the same data can be easily accomplished due to
the simplicity of the programming requirements.
Inputs of the paralleled M2732As may be con-
nected together when they are programmed with
the same data. A low level TTL pulse applied to the
E input programs the paralleled 2732As.
Program Inhibit
Programming of multiple M2732As in parallel with
different data is also easily accomplished. Except
for E, all like inputs (including GV
PP
) of the parallel
M2732As may be common. A TTL level program
pulse applied to a M2732A’s E input with GV
PP
at
21V will program that M2732A. A high level E input
inhibits the other M2732As from being pro-
grammed.
Program Verify
A verify should be performed on the programmed
bits to determine that they were correctly pro-
grammed. The verify is carried out with GV
PP
and
E at V
IL
.
ERASURE OPERATION
The erasure characteristics of the M2732A are
such that erasure begins when the cells are ex-
posed to light with wavelengths shorter than ap-
proximately 4000 Å. It should be noted that sunlight
and certain types of fluorescent lamps have wave-
lengths in the 3000-4000 Å range. Research shows
that constant exposure to room level fluorescent
lighting could erase a typical M2732A in approxi-
mately 3 years, while it would take approximately
1 week to cause erasure when exposed to the
direct sunlight. If the M2732A is to be exposed to
these types of lighting conditions for extended pe-
riods of time, it is suggested that opaque labels be
put over the M2732A window to prevent uninten-
tional erasure.
The recommended erasure procedure for the
M2732A is exposure to shortwave ultraviolet light
which has a wavelength of 2537 Å. The integrated
dose (i.e. UV intensity x exposure time) for erasure
should be a minimum of 15 W-sec/cm
2
. The era-
sure time with this dosage is approximately 15 to
20 minutes using an ultraviolet lamp with 12000
µW/cm
2
power rating. The M2732A should be
placed within 2.5 cm of the lamp tubes during
erasure. Some lamps have a filter on their tubes
which should be removed before erasure.
Table 3. Operating Modes
Mode
Read
Program
Verify
Program Inhibit
Standby
Note:
X = V
IH
or V
IL
.
E
V
IL
V
IL
Pulse
V
IL
V
IH
V
IH
GV
PP
V
IL
V
PP
V
IL
V
PP
X
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
Q0 - Q7
Data Out
Data In
Data Out
Hi-Z
Hi-Z
3/9
M2732A
AC MEASUREMENT CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
≤
20ns
0.45V to 2.4V
0.8V to 2.0V
Figure 4. AC Testing Load Circuit
1.3V
1N914
Note that Output Hi-Z is defined as the point where data
is no longer driven.
3.3kΩ
Figure 3. AC Testing Input Output Waveforms
DEVICE
UNDER
TEST
2.0V
0.8V
AI00827
OUT
CL = 100pF
2.4V
0.45V
CL includes JIG capacitance
AI00828
Table 4. Capacitance
(1)
(T
A
= 25
°C,
f = 1 MHz )
Symbol
C
IN
C
IN1
C
OUT
Parameter
Input Capacitance (except GV
PP
)
Input Capacitance (GV
PP
)
Output Capacitance
Test Condition
V
IN
= 0V
V
IN
= 0V
V
OUT
= 0V
Min
Max
6
20
12
Unit
pF
pF
pF
Note:
1. Sampled only, not 100% tested.
Figure 5. Read Mode AC Waveforms
A0-A11
tAVQV
E
tGLQV
G
tELQV
Q0-Q7
VALID
tAXQX
tEHQZ
tGHQZ
Hi-Z
DATA OUT
AI00782
4/9
M2732A
Table 5. Read Mode DC Characteristics
(1)
(T
A
= 0 to 70
°C
or –40 to 85
°C;
V
CC
= 5V
±
5% or 5V
±
10%; V
PP
= V
CC
)
Symbol
I
LI
I
LO
I
CC
I
CC1
V
IL
V
IH
V
OL
V
OH
Parameter
Input Leakage Current
Output Leakage Current
Supply Current
Supply Current (Standby)
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
I
OL
= 2.1mA
I
OH
= –400µA
2.4
Test Condition
Min
0
≤
V
IN
≤
V
CC
V
OUT
= V
CC
E = V
IL
, G = V
IL
E = V
IH
, G = V
IL
–0.1
2
Value
Max
±10
±10
125
35
0.8
V
CC
+ 1
0.45
µA
µA
mA
mA
V
V
V
V
Unit
Note:
1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
Table 6. Read Mode AC Characteristics
(1)
(T
A
= 0 to 70
°C
or –40 to 85
°C;
V
CC
= 5V
±
5% or 5V
±
10%; V
PP
= V
CC
)
Symbol
Alt
Parameter
Test
Condition
M2732A
-2, -20
Min
t
AVQV
t
ELQV
t
GLQV
t
EHQZ (2)
t
GHQZ
(2)
blank, -25
Min
Max
250
250
100
0
0
0
60
60
0
0
0
Min
-3
Max
300
300
150
130
130
0
0
0
Min
-4
Max
450
450
150
130
130
Unit
Max
200
200
100
t
ACC
t
CE
t
OE
t
DF
t
DF
t
OH
Address Valid to
Output Valid
Chip Enable Low to
Output Valid
Output Enable Low
to Output Valid
Chip Enable High to
Output Hi-Z
Output Enable High
to Output Hi-Z
Address Transition to
Output Transition
E = V
IL
,
G = V
IL
G = V
IL
E = V
IL
G = V
IL
E = V
IL
E = V
IL
,
G = V
IL
0
0
0
ns
ns
ns
ns
ns
ns
60
60
t
AXQX
Notes:
1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Sampled only, not 100% tested.
5/9
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