SaRonix
Crystal Clock Oscillator
Technical Data
Frequency Range:
Full Size:
Half Size:
Frequency Stability:
* 1 year @ +40°C
Temperature Range:
Operating:
Storage:
Supply Voltage:
Recommended Operating:
Supply Current:
ACTUAL SIZE
3.3 & 5V, HCMOS, ACMOS, TTL
STA / STT Series
STT 5V
250kHz - 135MHz
250kHz - 135MHz
STA 5V
125kHz - 135MHz
500kHz - 135MHz
STA 3.3V
125kHz - 125MHz
500kHz - 125MHz
±20, ±25, ±50 or ±100 ppm over all conditions: calibration
tolerance, operating temperature, rated input voltage change,
load change, aging*, shock and vibration
0 to +70°C or -40 to +85°C
-55 to +125°C
+5V ±10% or 3.3V ±10% (STA only)
50mA typ, 70mA max @ 5V or 30mA typ, 45mA max @ 3.3V
Description
A crystal controlled, low current, low
jitter and high frequency oscillator with
precise rise and fall times demanded in
high performance networking, telecom
and processor applications. The tri-state
function enables the output to go high
impedance. Available in a 14 or an 8 pin
DIP compatible, resistance welded, all
metal case. Pin 7 (or Pin 4) is grounded to
case to reduce EMI. See photo above for
new, full size metal package with a true
SMD adapter. For this package option
select option S in part number builder.
Applications & Features
• Fibre Channel
• Gigabit Ethernet
• High performance Processors
• True SMD DIL14 version available
• High Drive HCMOS, ACMOS or TTL
capability
• Tri-State output
• Precise Rise/Fall Times
• Reduced EMI circuitry
• Short circuit protected output
Output Drive:
ACMOS / TTL
Symmetry:
Rise & Fall Times:
Logic 0:
Logic 1:
Load:
Period Jitter RMS:
Mechanical:
Shock:
Solderability:
Terminal Strength:
Vibration:
Solvent Resistance:
Resistance to Soldering Heat:
See Part Numbering Guide
See Part Numbering Guide
10% V
DD
or 0.5V max
90% V
DD
or 2.5Vmin
50Ω ACMOS, 95Ω ACMOS @ 3.3V, 50mA sink & source @ TTL
8ps max
MIL-STD-883, Method 2002, Condition B
MIL-STD-883, Method 2003
MIL-STD-202, Method 211, Conditions B2
MIL-STD-883, Method 2007, Condition A
MIL-STD-202, Method 215
MIL-STD-202, Method 210, Condition A, B or C
Environmental:
Gross Leak Test:
Fine Leak Test:
Thermal Shock:
Moisture Resistance:
MIL-STD-883,
MIL-STD-883,
MIL-STD-883,
MIL-STD-883,
Method
Method
Method
Method
1014, Condition C
1014, Condition A2
1011, Conditions A
1004
Part Numbering Guide
STA A 9 9 B
Series
STA = ACMOS compatible, 3.3 or 5V
STT = TTL compatible, 5V only
Symmetry
0 = 40/60% max, 0 to +70°C
A = 45/55% max, 0 to +70°C
STT to 80 MHz max only
STA 3.3V to 109.9999 MHz max only
2 = 40/60% max, -40 to +85°C
STA 3.3V to 109.9999 MHz max only
3
- 90.0000
Frequency (MHz)
Supply
blank = 5V (STA or STT, 135MHz max)
3 = 3.3V (STA only, 125MHz max)
Stability Tolerance
AA = ±20ppm, 80MHz max, 0 to +70°C only
A = ±25ppm, 80MHz max, 0 to +70°C only
B = ±50ppm
C = ±100ppm
Package Size / Style
0 = Full Size
9 = ½ Size
K = Full Size, Gull Wing
J = ½ Size, Gull Wing
N = ½ Size, Gull Wing, Spanked Leads
S = Full Size, True SMD Adapter
Standard
*
Rise/Fall Times
1 = STT 4.0ns max 250kHz to 15 MHz full, to 35 MHz ½ size
2 = STT 2.0ns max from 15+ MHz full, 35+ MHz ½ size to 60 MHz
3 = STT 1.0ns max from 60+ MHz to 135 MHz
7 = STA 5.5ns max, 125kHz to 15 MHz full, 500kHz to 35 MHz ½ size
8 = STA 3.5ns max from 15+ MHz full, 35+ MHz ½ size to 60 MHz
9 = STA 2ns max from 60+ MHz to 135 MHz(5V), to 125 MHz(3.3V)
*
R/F times are standard with given frequency ranges, non-standard R/F times available on some models, please contact SaRonix
Example PN: STT220C - 60.0000
DS-108
REV K
SaRonix
www.pericom.com/saronix
SaRonix
Crystal Clock Oscillator
Technical Data
Package Details
FULL SIZE PACKAGE
ACMOS
0.9
.036
max
21.0
max
.825
5.08 max
.200
.46±.08
.018±.003
15.24±.13
.600±.005
Pin 1
Tri-State
Control
Pin 7
GND
6.35±.51
.250±.020
LOGIC 1
80% V
DD
50% V
DD
20% V
DD
LOGIC 0
SYMMETRY
SYMMETRY
2.5 VDC
1.5 VDC
0.5 VDC
GND
T
r
T
f
T
r
TTL
T
f
V
DD
3.3 & 5V, HCMOS, ACMOS, TTL
STA / STT Series
Output Waveform
Tri-State Logic Table
Pin 1 Input
Logic 1 or NC
Logic 0 or GND
Output
Standard Logic
Oscillation
High Impedance
Required Input Levels on Pin 1:
Logic 1 = 2.2V min
Logic 0 = 0.8V max
13.0
.510
max
Test Circuit
TEST
POINT
Pin 14
+5 or +3.3 VDC
(4) Glass
Insulators
7.75 max
.305
Pin 8
Output
mA
M
Pin 14 (8)
V
CC
POWER
SUPPLY
.01 µF
OUT
ACMOS
50Ω Load
Pin 8 (5)
Marking Format
**
Includes Date Code, Frequency & Part Number
56Ω
SARONIX
XTAL OSC
OSCILLATOR
GND
0.01 µF
VM
Pin 1 ( 1 )*
Pin 7 (4)
Denotes Pin 1
HALF SIZE PACKAGE
13.0
max
.510
0.9
max
.036
5.08
max
.200
6.35±.51
.250±.020
7.62±.20
.300±.008
Pin 4
GND
TRI-STATE INPUT
(current limited on fixture)
*
( ) Indicates pin numbers for half-size package
50Ω ACMOS TEST CIRCUIT (5V operation)
Ω
.46±.08
.018±.003
Pin 1
Tri-State
1.5
.059
TEST
POINT
mA
M
Pin 14 (8)
V
CC
POWER
SUPPLY
.01 µF
OUT
ACMOS
95Ω Load
Pin 8 (5)
95Ω
13.0
.510
max
120°
120°
120°
7.62±.20
.300±.008
OSCILLATOR
GND
0.01 µF
VM
Pin 1 ( 1 )*
Pin 14
+5 or +3.3 VDC
Glass Insulators
Pin 5
Output
Pin 7 (4)
Marking Format
**
Includes Date Code, Frequency & Part Number
SARONIX
TRI-STATE INPUT
(current limited on fixture)
*
( ) Indicates pin numbers for half-size package
Denotes Pin 1
95Ω ACMOS TEST CIRCUIT (3.3V operation)
Ω
**
Exact location of items may vary
All specifications are subject to change without notice.
mm
Scale: None (Dimensions in
)
inches
DS-108
REV K
SaRonix
www.pericom.com/saronix
FPGA/CPLD
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