HI-3182, HI-3183, HI-3184
HI-3185, HI-3186, HI-3188
March 2008
ARINC 429 Differential Line Driver
PIN CONFIGURATION
V
REF
1
GND (See Note * ) 2
SYNC 3
DATA (A) 4
C
A
5
A
OUT
6
-V 7
14 V
1
13 CLOCK
12 DATA (B)
11 C
B
10 B
OUT
9 +V
8 GND
GENERAL DESCRIPTION
The HI-3182, HI-3183, HI-3184, HI-3185, HI-3186 and HI-3188
bus interface products are silicon gate CMOS devices designed
as a line driver in accordance with the ARINC 429 bus specifica-
tions. In addition to being functional upgrades of Holt's HI-8382
& HI-8383 products, they are also alternate sources for the
HS-3182 ( Intersil/Harris), the RM3182 (Fairchild /Raytheon)
and a variety of similar line driver products from other manufac-
turers.
Inputs are provided for clocking and synchronization. These
signals are AND'd with the DATA inputs to enhance system
performance and allow the HI-318X series of products to be
used in a variety of applications. Both logic and synchronization
inputs feature built-in 2,000V minimum ESD input protection as
well as TTL and CMOS compatibility.
The differential outputs of the HI-318X series of products are
programmable to either the high speed or low speed ARINC 429
output rise and fall time specifications through the use of two
external capacitors. The output voltage swing is also adjustable
by the application of an external voltage to the VREF input.
Products with 0, 13 or 37.5 ohm resistors in series with each
ARINC output are available. In addition, the HI-3182 and
HI-3184 products also have a fuse in series with each output.
The HI-318X series of line drivers are intended for use where
logic signals must be converted to ARINC 429 levels such as
when using an ASIC, the HI-3282/HI-8282A ARINC 429 Serial
Transmitter/Dual Receiver, the HI-6010 ARINC 429 Transmit-
ter/Receiver or the HI-8783 ARINC Interface Device.
Holt
products are readily available for both industrial and military
applications. Please contact the Holt Sales Department for
additional information.
(Top View)
HI-3184PS, HI-3185PS & HI-3186PS
14 - PIN PLASTIC SMALL OUTLINE (ESOIC)
**
NB
Notes: * Pin 2 may be left floating
** Thermally Enhanced SOIC Package
(See Page 6 for additional package pin configurations)
FUNCTION
+
_
ARINC 429 DIFFERENTIAL LINE DRIVER
FEATURES
!
Low power CMOS
!
TTL and CMOS compatible inputs
!
Programmable output voltage swing
!
Adjustable ARINC rise and fall times
!
Plastic 14 & 16-pin thermally enhanced SOIC
packages available
!
Pin-for-Pin alternative for Intersil/Fairchild
applications
!
Operates at data rates up to 100 Kbits
!
Overvoltage protection
!
Industrial and extended temperature ranges
TRUTH TABLE
SYNC CLOCK DATA(A) DATA(B) AOUT
X
L
H
H
H
H
L
X
H
H
H
H
X
X
L
L
H
H
X
X
L
H
L
H
0V
0V
0V
-V
REF
+V
REF
0V
BOUT COMMENTS
0V
0V
0V
+V
REF
-V
REF
0V
NULL
NULL
NULL
LOW
HIGH
NULL
(Ds3182 Rev. K )
HOLT INTEGRATED CIRCUITS
www.holtic.com
03/09
HI-3182, HI-3183, HI-3184, HI-3185, HI-3186, HI-3188
FUNCTIONAL DESCRIPTION
The SYNC and CLOCK inputs establish data synchronization
utilizing two AND gates, one for each data input (figure 2).
Each logic input, including the power enable (STROBE) input,
are TTL/CMOS compatible.
Figure 1 illustrates a typical ARINC 429 bus application.
Three power supplies are necessary to operate the HI-3182;
typically +15V, -15V and +5V. The chip also works with ±12V
supplies. The +5V supply can also provide a reference
voltage that determines the output voltage swing. The
differential output voltage swing will equal 2V
REF
. If a value of
V
REF
other than +5V is needed, a separate +5V power supply
is required for pin V
1
.
With the DATA (A) input at a logic high and DATA (B) input at a
logic low, A
OUT
will switch to the +V
REF
rail and B
OUT
will
switch to the -V
REF
rail (ARINC HIGH state). With both data
input signals at a logic low state, the outputs will both switch to
0V (ARINC NULL state).
The driver output impedance, R
OUT
, is nominally 75, 26 or 0
ohms depending on the option chosen. The rise and fall times
of the outputs can be calibrated through the selection of two
external capacitor values that are connected to the C
A
and C
B
input pins. Typical values for high-speed operation
(100KBPS) are C
A
= C
B
= 75pF and for low-speed operation
(12.5 to 14KBPS) C
A
= C
B
= 500pF.
The C
A
and C
B
pins swing between +5V and ground allowing
the switching of capacitor values with an external single-
supply analog switch.
The ARINC outputs can be put in a tri-state mode by applying
a logic high to the STROBE input pin. If this feature is not
being used, the pin should be tied to ground. The STROBE
function is not available in the 14 & 16-pin SOIC package
configurations where the pin is internally connected to
ground.
The ARINC outputs of the HI-3182 and HI-3184 are protected
by internal fuses capable of sinking between 800 - 900 mA for
short periods of time (125
m
s).
The Vref pin has an internal pull-up resistor to V+, allowing the
use of a simple external zener diode to set the reference
voltage.
POWER SUPPLY SEQUENCING
The power supplies should be controlled to prevent large
currents during supply turn-on and turn-off. The
recommended sequence is +V followed by V
1
, always
ensuring that +V is the most positive supply. The -V supply
is not critical and can be asserted at any time.
+5V
+15V
V
REF
DATA (A)
V1
SYNC
CLOCK
A
OUT
+V
INPUTS
DATA (B)
CA
CB
STROBE
GND
-V
TO ARINC BUS
B
OUT
-15V
Figure 1.
ARINC 429 BUS APPLICATION
V
REF
+V
C
A
Shorted on
HI-3186, HI-3188
A
OUT
DATA (A)
LEVEL SHIFTER
AND SLOPE
CONTROL (A)
CLOCK
24.5W
OUTPUT
DRIVER (A)
C
L
SYNC
LEVEL SHIFTER
AND SLOPE
CONTROL (B)
24.5W
OUTPUT
DRIVER (B)
13W
R
L
13W
F
A
F
B
DATA (B)
V
1
STROBE
CURRENT
REGULATOR
Shorted on
HI-3183, HI-3186
HI-3188
Shorted on
HI-3183, HI-3185
HI-3186, HI-3188
GND
-V
C
B
B
OUT
Figure 2.
FUNCTIONAL BLOCK DIAGRAM
HOLT INTEGRATED CIRCUITS
2
HI-3182, HI-3183, HI-3184, HI-3185, HI-3186, HI-3188
PIN DESCRIPTIONS
SYMBOL
V
REF
STROBE
SYNC
DATA (A)
C
A
A
OUT
-V
GND
+V
B
OUT
C
B
DATA (B)
CLOCK
V
1
FUNCTION
ANALOG
INPUT
INPUT
INPUT
INPUT
OUTPUT
POWER
POWER
POWER
OUTPUT
INPUT
INPUT
INPUT
POWER
DESCRIPTION
Ref. voltage used to determine output voltage swing. Pin sources current to allow use of a zener reference.
A logic high tri-states the ARINC outputs. Not available in the 14-pin SOIC package (tied to GND internally).
Synchronizes data inputs
Data input terminal A
Connection for DATA (A) slew-rate capacitor
ARINC output terminal A
-12V to -15V
0.0V
+12V to +15V
ARINC output terminal B
Connection for DATA (B) slew-rate capacitor
Data input terminal B
Synchronizes data inputs
+5V ±5%
ABSOLUTE MAXIMUM RATINGS
All Voltages referenced to GND, TA = Operating Temperature Range (unless otherwise specified)
PARAMETER
Differential Voltage
Supply Voltage
SYMBOL
V
DIF
+V
-V
V
1
V
REF
V
IN
CONDITIONS
Voltage between +V and -V terminals
OPERATING RANGE
MAXIMUM
40
UNIT
V
V
V
V
V
V
V
V
+10.8 to +16.5
-10.8 to -16.5
+5 ±5%
For ARINC 429
For Applications other than ARINC
+5 ±5%
1.5 to 6
+7
6
6
> GND -0.3
< V1 +0.3
Voltage Reference
Input Voltage Range
Output Short-Circuit Duration
Output Overvoltage Protection
Operating Temperature Range
Storage Temperature Range
Lead Temperature
Junction Temperature
See Note: 1
See Note: 2
T
A
T
STG
Industrial
Extended
Ceramic & Plastic
Soldering, 10 seconds
T
J
-40 to +85
-55 to +125
-65 to +150
+275
+175
°C
°C
°C
°C
°C
Note 1. Heatsinking may be required for continuous Output Short Circuit at +125°C and for 100KBPS at +125°C.
Note 2. The fuses used for Output Overvoltage Protection may be blown by the presence of a voltage at either output that is greater
than ±12.0V with respect to GND. (HI-3182 & 3184 only)
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings
only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
HOLT INTEGRATED CIRCUITS
3
HI-3182, HI-3183, HI-3184, HI-3185, HI-3186, HI-3188
DC ELECTRICAL CHARACTERISTICS
+V = +15V, -V = -15V, V
1
= V
REF
= +5.0V, T
A
= Operating Temperature Range (unless otherwise specified).
PARAMETER
Supply Current +V (Operating)
Supply Current -V (Operating)
Supply Current
V
1
(Operating)
Reference Pin Current
V
REF
(Operating)
Supply Current +V (During Short Circuit Test)
Supply Current -V (During Short Circuit Test)
Output Short Circuit Current (Output High)
Output Short Circuit Current (Output Low)
Input Current (Input High)
Input Current (Input Low)
Input Voltage High
Input Voltage Low
Output Voltage High (Output to Ground)
Output Voltage Low (Output to Ground)
Output Voltage Null
Input Capacitance
SYMBOL
I
CCOP
(+V)
I
CCOP
(-V)
I
CCOP
(
V
1
)
I
CCOP
(
V
REF
)
I
SC
(+V)
I
SC
(-V)
I
OHSC
I
OLSC
I
IH
I
IL
V
IH
V
IL
V
OH
V
OL
V
NULL
C
IN
No Load
No Load
No Load
CONDITION
(0 - 100KBPS)
(0 - 100KBPS)
(0 - 100KBPS)
MIN
-16
TYP
MAX UNITS
+16
500
mA
mA
µA
mA
mA
mA
-80
mA
mA
1.0
µA
µA
V
0.5
V
V
V
mV
pF
+V
REF
+.
25
-V
REF
+.
25
+250
No Load,
V
REF = 5V (0 - 100KBPS)
Short to Ground
Short to Ground
Short to Ground
Short to Ground
(See Note: 1)
(See Note: 1)
-1.0
-150
+80
-1.0
2.0
-0.4
-0.15
150
V
MIN
=0 (See Note: 2)
V
MIN
=0 (See Note: 2)
No Load
No Load
No Load
See Note 1
(0 -100KBPS)
(0 -100KBPS)
(0-100KBPS)
+V
REF
-.
25
-V
REF
-.
25
-250
15
Note 1. Not tested, but characterized at initial device design and after major process and/or design change which affects this parameter.
Note 2. Interchangeability of force and sense is acceptable.
AC ELECTRICAL CHARACTERISTICS
+V = +15V, -V = -15V, V
1
= V
REF
= +5.0V, T
A
= Operating Temperature Range (unless otherwise specified).
PARAMETER
Rise Time (
A
OUT
,
B
OUT
)
Fall Time (
A
OUT
,
B
OUT
)
Propagtion Delay Input to Output
Propagtion Delay Input to Output
SYMBOL
t
R
t
F
t
PLH
t
PHL
CONDITION
C
A
=
C
B
= 75pF
C
A
=
C
B
= 75pF
C
A
=
C
B
= 75pF
C
A
=
C
B
= 75pF
See Figure 3.
See Figure 3.
See Figure 3.
See Figure 3.
MIN
1.0
1.0
TYP
MAX UNITS
2.0
2.0
3.0
3.0
µs
µs
µs
µs
DATA (A) 0V
DATA (B) 0V
V
REF
50%
50%
ADJUST
BY
C
A
2.0V
0.5V
2.0V
0.5V
+4.75V to +5.25V
A
OUT
0V
ADJUST
BY
C
A
-V
REF
50%
50%
-4.75V to -5.25V
ADJUST
BY
C
B
ADJUST
BY
C
B
t
PHL
+V
REF
+4.75V to +5.25V
-4.75V to -5.25V
HIGH
NULL
B
OUT
0V
-V
REF
t
PLH
t
R
DIFFERENTIAL
OUTPUT 0V
2V
REF
+9.5V to +10.5V
(
A
OUT -
B
OUT
)
NOTE: OUTPUTS UNLOADED
t
F
-2V
REF
LOW
-9.5V to -10.5V
Figure 3.
SWITCHING WAVEFORMS
HOLT INTEGRATED CIRCUITS
4
HI-3182, HI-3183, HI-3184, HI-3185, HI-3186, HI-3188
HI-318X PACKAGE THERMAL CHARACTERISTICS
MAXIMUM ARINC LOAD
PACKAGE STYLE
1
3, 6, 7
HEAT SINK
Unsoldered
Soldered
Unsoldered
Soldered
N/A
ØJA
(°C/W)
82
65
51
28
70
SUPPLY CURRENT
20 mA
20 mA
20 mA
20 mA
25 mA
2
JUNCTION TEMPERATURE, Tj
TA = 25°C TA = 85°C TA = 125°C
57°C
51°C
45°C
36°C
56°C
117°C
111°C
105°C
96°C
110°C
157°C
151°C
145°C
136°C
150°C
14-pin Thermally
Enhanced Plastic
SOIC (ESOIC)
14-pin Thermally
Enhanced Plastic
SOIC (ESOIC)
28-pin Plastic
A
OUT
and B
OUT
Shorted to Ground
PACKAGE STYLE
1
3, 4, 5, 6, 7
HEAT SINK
Unsoldered
Soldered
Unsoldered
Soldered
N/A
ØJA
(°C/W)
82
65
51
28
70
SUPPLY CURRENT
36 mA
36 mA
40 mA
40 mA
63 mA
2
JUNCTION TEMPERATURE, Tj
TA = 25°C TA = 85°C TA = 125°C
57°C
78°C
64°C
53°C
100°C
147°C
138°C
124°C
113°C
150°C
187°C
178°C
164°C
153°C
182°C
14-pin Thermally
Enhanced Plastic
SOIC (ESOIC)
14-pin Thermally
Enhanced Plastic
SOIC (ESOIC)
28-pin Plastic
Notes:
1. All data taken in still air on devices soldered to a single layer copper PCB (3" X 4.5" X .062").
2. At 100% duty cycle, 15V power supplies. For 12V power supplies multiply all tabulated values by 0.8.
3. High Speed: Data Rate = 100 Kbps, Load: R = 400 Ohms, C = 10 nF. Data not presented for C = 30 nF
as this is considered unrealistic for high speed operation.
4. Similar results would be obtained with A
OUT
shorted to B
OUT
.
5. For applications requiring survival with continuous short circuit, operation above Tj = 175°C is not recommended.
6. Data will vary depending on air flow and the method of heat sinking employed.
7. Current values listed are for each of the +V and -V supplies.
HEAT SINK - ESOIC PACKAGES
Both the 14-pin and 16-pin thermally enhanced SOIC
packages are used for HI-318X products. These ESOIC
packages include a metal heat sink located on the bottom
surface of the device. This heat sink should be soldered
down to the printed circuit board for optimum thermal
dissipation. The heat sink is electrically isolated from the
chip and can be soldered to any ground or power plane.
However, since the chip’s substrate is at +V, connecting
the heat sink to this power plane is recommended to avoid
coupling noise into the circuit.
HOLT INTEGRATED CIRCUITS
5
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