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MM74C175MX

Description
D Flip-Flop, CMOS Series, 1-Func, Positive Edge Triggered, 4-Bit, Complementary Output, CMOS, PDSO16, 0.150 INCH, MS-012, SOIC-16
Categorylogic    logic   
File Size54KB,6 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
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MM74C175MX Overview

D Flip-Flop, CMOS Series, 1-Func, Positive Edge Triggered, 4-Bit, Complementary Output, CMOS, PDSO16, 0.150 INCH, MS-012, SOIC-16

MM74C175MX Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Parts packaging codeSOIC
package instructionSOP, SOP16,.25
Contacts16
Reach Compliance Codeunknown
seriesCMOS
JESD-30 codeR-PDSO-G16
JESD-609 codee0
length9.9 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeD FLIP-FLOP
Maximum Frequency@Nom-Sup2000000 Hz
MaximumI(ol)0.00036 A
Number of digits4
Number of functions1
Number of terminals16
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Output polarityCOMPLEMENTARY
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP16,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE
method of packingTAPE AND REEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5/15 V
propagation delay (tpd)300 ns
Certification statusNot Qualified
Maximum seat height1.75 mm
Maximum supply voltage (Vsup)15 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Trigger typePOSITIVE EDGE
width3.9 mm
minfmax5 MHz
Base Number Matches1
MM74C175 Quad D-Type Flip-Flop
October 1987
Revised January 1999
MM74C175
Quad D-Type Flip-Flop
General Description
The MM74C175 consists of four positive-edge triggered D-
type flip-flops implemented with monolithic CMOS technol-
ogy. Both are true and complemented outputs from each
flip-flop are externally available. All four flip-flops are con-
trolled by a common clock and a common clear. Informa-
tion at the D-type inputs meeting the set-up time
requirements is transferred to the Q outputs on the posi-
tive-going edge of the clock pulse. The clearing operation,
enabled by a negative pulse at Clear input, clears all four Q
outputs to logical “0” and Q's to logical “1”.
All inputs are protected from static discharge by diode
clamps to V
CC
and GND.
Features
s
Wide supply voltage range:
s
Guaranteed noise margin:
s
High noise immunity:
3V to 15V
1.0V
0.45 V
CC
(typ.)
Fan out of 2 driving 74L
s
Low power TTL compatibility:
Ordering Code:
Order Number
MM74C175M
MM74C175N
Package Number
M16A
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP and SOIC
Truth Table
Each Flip-Flop
Inputs
Clear
L
H
H
H
H
Clock
X
H
L
D
X
H
L
X
X
Outputs
Q
L
H
L
NC
NC
Q
H
L
H
NC
NC
H
=
HIGH Level
L
=
LOW Level
X
=
Irrelevant
↑ =
Transition from LOW-to-HIGH level
NC
=
No Change
Top View
© 1999 Fairchild Semiconductor Corporation
DS005900.prf
www.fairchildsemi.com
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