K7D403671M
K7D401871M
FEATURES
• 128Kx36 or 256Kx18 Organizations.
• 2.5V Core/1.5V Output Power Supply.
• HSTL Input and HSTL Outputs.
• Single Differential HSTL Clock.
• Synchronous Pipeline Mode of Operation with Self-Timed
Late Write.
• Free Running Active High and Active Low Echo Clock Output
Pin.
• Asynchronous Output Enable.
• Registered Addresses, Burst Control Inputs and Data Inputs.
• Registered Outputs.
• Single and Double Data Rate Burst Read and Write.
• 4 Count Burst Operation
• JTAG 1149.1 Compatible Test Access port.
• 153(9x17) Pin Ball Grid Array Package(14mm x 22mm).
128Kx36 & 256Kx18 SRAM
• Programmable Impedance Output Drivers.
Organization
Part Number
K7D403671M-H25
128Kx36
K7D403671M-H22
K7D403671M-H20
K7D403671M-H16
K7D401871M-H25
256Kx18
K7D401871M-H22
K7D401871M-H20
K7D401871M-H16
Cycle
Time
4
44
5
6
4
44
5
6
Access
Time
2.4
2.4
2.7
3.3
2.4
2.4
2.7
3.3
FUNCTIONAL BLOCK DIAGRAM
SA[0:16]( or SA[0:17])
Address
Register
CE
17(or 18)
15(or 16)
(Burst Address)
Burst
Counter
(Burst Write
Address)
17(or 18)
15(or 16)
36(or 18)x2
2 : 1 MUX
Write Buffer
CE
R/W
LD
Internal
Clock
Generator
G
Data Output Strobe
Data Output Enable
State Machine
36(or 18)
DATA
KQ,KQ
XDIN
Strobe_out
Output
Buffer
Echo Clock
Output
Data In
Register
(2 stage)
Memory Array
128Kx36
or
(256Kx18)
36(or 18)x2
S/A Array
Write
Address
Register
(2 stage)
CE
Synchronous
Select
&
R/W control
2:1
MUX
Dec.
Data Out
K,K
Clock
Buffer
Data In
36(or 18)x2
W/D
Array
36(or 18)x2
Comparator
B
1
B
3
Advance
Co
Control
SD/DD
B
2
PIN DESCRIPTION
Pin Name
K, K
SA
SA
0
, SA
1
DQ
V
DD
V
DDQ
V
REF
B
1
B
2
B
3
KQ, KQ
Pin Description
Differential Clocks
Synchronous Address Input
Synchronous Burst Address Input
Synchronous Data I/O
Core Power Supply
Output Power Supply
HSTL Input Reference Voltage
Load External Address
Burst R/W Enable
Single/Double Data Selection
Differential Output Echo Clocks
Pin Name
G
TCK
TMS
TDI
TDO
ZQ
LBO
MODE
V
SS
NC
Pin Description
Asynchronous Output Enable
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
Output Driver Impedance Control Input
Linear Burst Order
No Connect (Reserved)
GND
No Connection
2
Rev 1.0
Nov. 1999
K7D403671M
K7D401871M
FUNCTION DESCRIPTION
128Kx36 & 256Kx18 SRAM
The K7D403671M and K7D401871M are 4,718,592 bit Synchronous Pipeline Burst Mode SRAM devices. They are organized as
131,072 words by 36 bits for K7D403671M and 262,144 words by 18 bits for K7D401871M, fabricated using Samsung's advanced
CMOS technology.
Single differential HSTL level K clocks are used to initiate the read/write operation and all internal operations are self-timed. At the
rising edge of K clock, all addresses and burst control inputs are registered internally. And data inputs are registered at rising edges
of K clock for a single data controlled mode, or at rising and falling edges of K clock for a dual data controlled mode, in the following
cycle after write addresses are asserted.
An internal write data buffer allows write data to be stored before loaded into memory core in the next write cycles. Data outputs are
updated from output registers on the rising edges of K clock for a single data controlled mode, or on the rising and falling edges of
the K clock for a dual data controlled mode. Read data is referenced to Echo clock outputs. The chip is operated with a single +2.5V
power supply and is compatible with HSTL input and HSTL output. The package is 9x17(153) Ball Grid Array balls on a 1.27mm
pitch.
Read Operation(Single and Double)
During single read operation, the address is registered during the first clock edge, the internal array is read between this first edge
and second edge, it is read again in the following cycle from the address increased by burst counter, and data is captured in the out-
put register driven to the CPU during the second clock high edge and third clock high edge. During double read operation, the
address is registered during the first clock edge, the internal array is read twice as much as wider than external bits, transfered to
dout buffer sequentially by burst order and the following cycle the same operation occur from address increased by burst counter,
and data is captured in the output register driven to the CPU at active high clock edge and active low clock edge.
During consecutive read cycles where the address is the same, the data output must be held constant without any glitches. This
characteristic is because the SRAM will be read by devices that will operate slower than the SRAM frequency and will require multi-
ple SRAM cycles to perform a single read operation.
Write(Store) Operation
All addresses and R/W are sampled with B
1
and B
2
on the clock rising edge. B
1
and B
2
are low on the rising clock. Write address is
sampled on the rising clock, one cycle after write address and Din have been sampled by the SRAM during 2 consecutive cycles at
each active high and low clock edge and stored to write buffer for next real writing array. Actual write is done by using write data
buffer on the SRAM that capture the write addresses on one address write cycles, and write the array on the next address write
cycles. The "next address write cycles" can actually be many cycles away, broken by a series of read cycles. The SRAM is able to
write 72 bits per cycle with 2-prefetched write buffer. This alleviates timing penalty of read after write cycle.
Echo clock operation
To assure the output tracibility, the SRAM provides the output Echo clock, pair of complement clock, which is synchronized with inter-
nal data output.
During read and write cycle, the Echo clock is triggered by internal output clock signal, and transfered to external through same struc-
tures as output driver in read cycle.
Bypass Read Operation
Since write data is not fully written into the array on first write cycle, there is a need to sense the address in case a future read is to
be done from the location that has not been written yet. For this case, the address comparator check to see if the new read address
is the same as the contents of the stored write address latch. If the contents match, the read data must be supplied from the stored
write data latch with standard read timing. If there is no match, the read data comes from the SRAM array.
PROGRAMMABLE IMPEDANCE OUTPUT BUFFER OPERATION
The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to V
SS
through a precision resistor(RQ).
The value of RQ is five times the output impedance desired. For example, 250Ω resistor will give an output impedance of 50Ω. The
allowable range of RQ is between 175Ω and 350Ω. Impedance updates occur early in cycles that do not activate the outputs, such
as deselect cycles. They may also occur in cycles initiated with G high. In all cases impedance updates are transparent to the user
and do not produce access time "push-outs" or other anomalous behavior in the SRAM. Periodic readjustment is necessary as the
impedance is greatly affected by drifts in supply voltage and temperature. Impedance updates occur no more often than every 32
clock cycles. Clock cycles are counted whether the SRAM is selected or not and proceed regardless of the type of cycle being exe-
cuted. Therefore, the user can be assured that after 33 continuous read cycles have occurred, an impedance update will occur the
next time G are high at a rising edge of the K clock. There are no power up requirements for the SRAM. However, to guarantee opti-
mum output driver impedance after power up, the SRAM needs 1024 non-read cycles.
4
Rev 1.0
Nov. 1999
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