3256A datasheet, PDF - EEWORLD Datasheet

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3256A: DescriptionEE PLD, 18 ns, PQFP160; Categorysemiconductor Programmable logic devices; File Size126KB，13 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com

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3256A Overview

EE PLD, 18 ns, PQFP160

3256A Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	160
Maximum operating temperature	70 Cel
Minimum operating temperature	0.0 Cel
Maximum supply/operating voltage	5.25 V
Minimum supply/operating voltage	4.75 V
Rated supply voltage	5 V
Number of input and output buses	128
Processing package description	Plastic, Quad Flat Package-160
state	DISCONTINUED
Craftsmanship	CMOS
packaging shape	SQUARE
Package Size	FLATPACK
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	0.6500 mm
terminal coating	tin lead
Terminal location	Four
Packaging Materials	Plastic/Epoxy
Temperature level	COMMERCIAL
organize	0 DEDICATED INPUTS, 128 I/O
Maximum FCLK clock frequency	50 MHz
Output function	MACROCELL
Programmable logic type	electronic programmable logic devices
propagation delay TPD	18 ns
Dedicated input quantity	0.0

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ispLSI 3256A

In-System Programmable High Density PLD

Features

• HIGH-DENSITY PROGRAMMABLE LOGIC

— 128 I/O Pins

— 11000 PLD Gates

— 384 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

• HIGH-PERFORMANCE E

CMOS

TECHNOLOGY

—

max

= 90 MHz Maximum Operating Frequency

—

= 12 ns Propagation Delay

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

• IN-SYSTEM PROGRAMMABLE

— 5V In-System Programmable (ISP™) using Lattice

ISP or Boundary Scan Test (IEEE 1149.1) Protocol

— Increased Manufacturing Yields, Reduced Time-to-

Market, and Improved Product Quality

— Reprogram Soldered Devices for Faster Debugging

• 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

— Enhanced Pin Locking Capability

— Five Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to Mini-

mize Switching Noise

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

Functional Block Diagram

Output Routing Pool

D Q

Boundary

Scan

AND Array

Array

D Q

Twin

GLB

D Q

Output Routing Pool

D Q

Array

D Q

Global Routing Pool

Output Routing Pool

0139A

Description

The ispLSI 3256A is a High-Density Programmable Logic

Device containing 384 Registers, 128 Universal I/O pins,

five Dedicated Clock Input Pins, eight Output Routing

Pools (ORP) and a Global Routing Pool (GRP) which

allows complete inter-connectivity between all of these

elements. The ispLSI 3256A features 5V in-system

programmability and in-system diagnostic capabilities.

The ispLSI 3256A offers non-volatile reprogrammability

of the logic, as well as the interconnect to provide truly

reconfigurable systems.

The basic unit of logic on the ispLSI 3256A device is the

Twin Generic Logic Block (Twin GLB) labelled A0, A1...H3.

There are a total of 32 Twin GLBs in the ispLSI 3256A

device. Each Twin GLB has 24 inputs, a programmable

AND array and two OR/Exclusive-OR Arrays, and eight

outputs which can be configured to be either combinato-

rial or registered. All Twin GLB inputs come from the

GRP.

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

May 1999

3256a_09

Output Routing Pool

3256A Related Products

	3256A	ispLSI3256A-50LM	ispLSI3256A-70LQ	ispLSI3256A-50LMI	ispLSI3256A-70LQI	ispLSI3256A-90LQ
Description	EE PLD, 18 ns, PQFP160	EE PLD, 18 ns, PQFP160	EE PLD, 18 ns, PQFP160	EE PLD, 18 ns, PQFP160	EE PLD, 18 ns, PQFP160	EE PLD, 15 ns, PQFP160
Number of terminals	160	160	160	160	160	160
Maximum operating temperature	70 Cel	70 °C	70 °C	85 °C	85 °C	70 °C
surface mount	Yes	YES	YES	YES	YES	YES
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal location	Four	QUAD	QUAD	QUAD	QUAD	QUAD
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL
organize	0 DEDICATED INPUTS, 128 I/O	0 DEDICATED INPUTS, 128 I/O	0 DEDICATED INPUTS, 128 I/O	0 DEDICATED INPUTS, 128 I/O	0 DEDICATED INPUTS, 128 I/O	0 DEDICATED INPUTS, 128 I/O
Output function	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL
Programmable logic type	electronic programmable logic devices	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD
Is it Rohs certified?	-	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	-	Lattice	Lattice	Lattice	Lattice	Lattice
Parts packaging code	-	QFP	QFP	QFP	QFP	QFP
package instruction	-	MQFP-160	PLASTIC, QFP-160	MQFP-160	PLASTIC, QFP-160	PLASTIC, QFP-160
Contacts	-	160	160	160	160	160
Reach Compliance Code	-	unknow	_compli	unknow	_compli	unknow
ECCN code	-	EAR99	EAR99	EAR99	EAR99	EAR99
Other features	-	YES	YES	YES	YES	YES
maximum clock frequency	-	37 MHz	50 MHz	37 MHz	50 MHz	61 MHz
In-system programmable	-	YES	YES	YES	YES	YES
JESD-30 code	-	S-MQFP-G160	S-PQFP-G160	S-MQFP-G160	S-PQFP-G160	S-PQFP-G160
JTAG BST	-	YES	YES	YES	YES	YES
length	-	27.69 mm	28 mm	27.69 mm	28 mm	28 mm
Humidity sensitivity level	-	1	3	1	3	3
Number of I/O lines	-	128	128	128	128	128
Number of macro cells	-	256	256	256	256	256
Package body material	-	METAL	PLASTIC/EPOXY	METAL	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	-	QFP	QFP	QFP	QFP	QFP
Encapsulate equivalent code	-	QFP160,1.2SQ	QFP160,1.2SQ	QFP160,1.2SQ	QFP160,1.2SQ	QFP160,1.2SQ
Package shape	-	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	-	FLATPACK	FLATPACK	FLATPACK	FLATPACK	FLATPACK
Peak Reflow Temperature (Celsius)	-	225	225	225	225	225
power supply	-	5 V	5 V	5 V	5 V	5 V
propagation delay	-	24.5 ns	18 ns	24.5 ns	18 ns	15 ns
Certification status	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	-	3.96 mm	4.1 mm	3.96 mm	4.1 mm	4.1 mm
Maximum supply voltage	-	5.25 V	5.25 V	5.5 V	5.5 V	5.25 V
Minimum supply voltage	-	4.75 V	4.75 V	4.5 V	4.5 V	4.75 V
Nominal supply voltage	-	5 V	5 V	5 V	5 V	5 V
technology	-	CMOS	CMOS	CMOS	CMOS	CMOS
Terminal pitch	-	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm
Maximum time at peak reflow temperature	-	NOT SPECIFIED	30	NOT SPECIFIED	30	30
width	-	27.69 mm	28 mm	27.69 mm	28 mm	28 mm

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