Data Sheet
FEATURES
Differential ECL-compatible outputs
700 ps propagation delay input to output
75 ps propagation delay dispersion
Input common-mode range: –2.0 V to +3.0 V
Robust input protection
Differential latch control
Internal latch pull-up resistors
Power supply rejection greater than 85 dB
700 ps minimum pulse width
1.5 GHz equivalent input rise time bandwidth
Typical output rise/fall time of 500 ps
ESD protection > 4kV HBM, >200V MM
Programmable hysteresis
Dual, High Speed ECL Comparators
ADCMP563/ADCMP564
FUNCTIONAL BLOCK DIAGRAMS
HYS*
NONINVERTING
INPUT
Q OUTPUT
ADCMP563/
ADCMP564
INVERTING
INPUT
Q OUTPUT
*ADCMP564 ONLY
Figure 1.
QA
1
QA
2
GND
3
LEA
4
LEA
5
V
EE 6
–INA
7
+INA
8
16
QB
15
QB
14
GND
APPLICATIONS
Automatic test equipment
High speed instrumentation
Scope and logic analyzer front ends
Window comparators
High speed line receivers
Threshold detection
Peak detection
High speed triggers
Patient diagnostics
Hand-held test instruments
Zero crossing detectors
Line receivers and signal restoration
Clock drivers
ADCMP563
BRQ
TOP VIEW
(Not to Scale)
13
LEB
12
LEB
11
V
CC
04650-0-002
10
–INB
9
+INB
Figure 2.
ADCMP563
16-Lead QSOP
GND
1
QA
2
QA
3
GND
4
LEA
5
LEA
6
V
EE 7
–INA
8
+INA
9
HYSA
10
20
19
18
GND
QB
QB
GND
LEB
LEB
V
CC
–INB
04650-0-012
ADCMP564
BRQ
TOP VIEW
(Not to Scale)
17
16
15
14
13
12
11
GENERAL DESCRIPTION
The
ADCMP563/ADCMP564
are high speed comparators
fabricated on Analog Devices’ proprietary XFCB process. The
devices feature a 700 ps propagation delay with less than 75 ps
overdrive dispersion. Dispersion, a measure of the difference in
propagation delay under differing overdrive conditions, is a partic-
ularly important characteristic of high speed comparators. A separate
programmable hysteresis pin is available on the
ADCMP564.
A differential input stage permits consistent propagation delay
with a wide variety of signals in the common-mode range from
−2.0 V to +3.0 V. Outputs are complementary digital signals that
are fully compatible with ECL 10 K and 10 KH logic families.
The outputs provide sufficient drive current to directly drive
transmission lines terminated in 50 Ω to −2 V. A latch input,
which is included, permits tracking, track-and-hold, or sample-
and-hold modes of operation. The latch input pins contain internal
pull-ups that set the latch in tracking mode when left open.
The
ADCMP563/ADCMP564
are specified over the industrial
temperature range (−40°C to +85°C).
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
+INB
HYSB
15
LEA
14
LEA
–INA 1
+INA 2
+INB 3
–INB 4
13
GND
16
V
EE
Figure 3.
ADCMP564
20-Lead QSOP
12 QA
ADCMP563
BCP
TOP VIEW
(Not to Scale)
11 QA
10 QB
9
QB
GND
8
LEB
7
V
CC
5
LEB
6
04650-0-001
LATCH ENABLE
INPUT
LATCH ENABLE
INPUT
NOTES
1. THE EXPOSED PAD SHOULD BE EITHER CONNECTED TO VEE OR LEFT FLOATING.
Figure 4.
ADCMP563
16-Lead LFCSP
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2007–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
04650-0-026
ADCMP563/ADCMP564
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Specifications..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Thermal Considerations .............................................................. 5
ESD Caution .................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 8
Data Sheet
Timing Information ....................................................................... 10
Application Information ................................................................ 11
Clock Timing Recovery ............................................................. 11
Optimizing High Speed Performance ..................................... 11
Comparator Propagation Delay Dispersion ............................... 11
Comparator Hysteresis .............................................................. 12
Minimum Input Slew Rate Requirement ................................ 12
Typical Application Circuits ......................................................... 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 15
REVISION HISTORY
4/16—Rev. C to Rev. D
Changes to Figure 4 .......................................................................... 1
Changes to Figure 7 .......................................................................... 6
Updates Outline Dimensions ........................................................ 15
Changes to Ordering Guide .......................................................... 15
6/11—Rev. B to Rev. C
Changes to Figure 4 .......................................................................... 1
Changes to Figure 7 and LFCSP Pin Numbers (Table 3) ............ 6
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 15
5/05—Rev. A to Rev. B
Added 16-Lead LFCSP....................................................... Universal
Changes to Applications .................................................................. 1
Changes to Table 1.............................................................................3
Changes to Optimizing High Speed Performance Section ....... 11
Changes to Comparator Hysteresis Section ................................ 12
Changes to Minimum Input Slew Rate Requirement Section . 12
Changes to Ordering Guide .......................................................... 14
7/04—Rev. 0 to Rev. A
Changes to Specification Table ........................................................4
Changes to Figure 14.........................................................................9
Changes to Figure 21...................................................................... 12
Changes to Figure 23...................................................................... 13
4/04—Revision 0: Initial Version
Rev. D | Page 2 of 15
Data Sheet
SPECIFICATIONS
ADCMP563/ADCMP564
V
CC
= +5.0 V, V
EE
= −5.2 V, T
A
= −40°C to +85°C. Typical values are at T
A
= +25°C, unless otherwise noted.
Table 1. Electrical Characteristics
Parameter
DC INPUT CHARACTERISTICS
Input Voltage Range
Input Differential Voltage
Input Offset Voltage
Input Offset Voltage Channel Matching
Offset Voltage Temperature Coefficient
Input Bias Current
Input Bias Current Temperature Coefficient
Input Offset Current
Input Capacitance
Input Resistance, Differential Mode
Input Resistance, Common Mode
Active Gain
Common-Mode Rejection Ratio
Hysteresis
LATCH ENABLE CHARACTERISTICS
Latch Enable Voltage Range
Latch Enable Differential Input Voltage
Latch Enable Input High Current
Latch Enable Input Low Current
LE Voltage, Open
LE Voltage, Open
Latch Setup Time
Latch Hold Time
Latch to Output Delay
Latch Minimum Pulse Width
DC OUTPUT CHARACTERISTICS
Output Voltage—High Level
Output Voltage—Low Level
Rise Time
Fall Time
AC PERFORMANCE
Propagation Delay
Propagation Delay Temperature Coefficient
Prop Delay Skew—Rising Transition to Falling
Transition
Within Device Propagation Delay Skew—
Channel-to-Channel
Overdrive Dispersion
Slew Rate Dispersion
Pulse Width Dispersion
Duty Cycle Dispersion
Common-Mode Voltage Dispersion
Symbol
Conditions
Min
−2.0
−5
−10.0
Typ
Max
3.0
+5
+10.0
Unit
V
V
mV
mV
µV/°C
µA
nA/°C
µA
pF
kΩ
kΩ
dB
dB
mV
V
V
µA
µA
V
V
ps
ps
ps
ps
−0.81
−1.54
530
450
700
830
0.25
50
50
75
75
50
25
10
10
V
V
ps
ps
ps
ps
ps/°C
ps
ps
ps
ps
ps
ps
ps
ps
V
OS
∆V
OS
/d
T
I
BC
V
CM
= 0 V
@ −IN = −2 V, +IN = +3 V
−10.0
C
IN
A
V
CMRR
V
CM
= −2.0 V to +3.0 V
R
HYS
= ∞
−2.0
0.4
−300
−300
−0.2
−2.8
±2.0
±2.0
2.0
±3
0.5
±1.0
0.75
750
1800
63
80
±1.0
+10.0
t
S
t
H
t
PLOH
,
t
PLOL
t
PL
V
OH
V
OL
t
R
t
F
t
PD
∆t
PD
/d
T
@ 0.0 V
@ −2.0 V
Latch inputs not connected
Latch inputs not connected
V
OD
= 250 mV
V
OD
= 250 mV
V
OD
= 250 mV
V
OD
= 250 mV
ECL 50 Ω to −2.0 V
ECL 50 Ω to −2.0 V
10% to 90%
10% to 90%
V
OD
= 1 V
V
OD
= 20 mV
V
OD
= 1 V
V
OD
= 1 V
V
OD
= 1 V
20 mV ≤ V
OD
≤ 100 mV
100 mV ≤ V
OD
≤ 1.5 V
0.4 V/ns ≤ SR ≤ 1.33 V/ns
750ps ≤ PW ≤ 10 ns
33 MHz, 1 V/ns, 0.5 V
1 V swing, −1.5 V ≤ V
CM
≤ +2.5 V
0
−2.6
200
200
500
500
0
2.0
+300
+300
+0.1
−2.4
−1.15
−1.95
Rev. D | Page 3 of 15
ADCMP563/ADCMP564
Parameter
AC PERFORMANCE (Continued)
Equivalent Input Rise Time Bandwidth
1
Maximum Toggle Rate
Minimum Pulse Width
RMS Random Jitter
Unit to Unit Propagation Delay Skew
POWER SUPPLY
Positive Supply Current
Negative Supply Current
Positive Supply Voltage
Negative Supply Voltage
Power Dissipation
DC Power Supply Rejection Ratio—V
CC
DC Power Supply Rejection Ratio—V
EE
HYSTERESIS (ADCMP564 Only)
Hysteresis
Hysteresis Pin Bias Voltage
Hysteresis Pin Series Resistance
1
Data Sheet
Symbol
BW
EQ
PW
MIN
Conditions
0 V to 1 V swing, 2 V/ns
>50% output swing, 50% duty cycle
Δt
PD
< 25 ps
V
OD
= 400 mV, 1.3 V/ns, 312 MHz,
50% duty cycle
Min
Typ
1500
800
700
1.0
100
I
VCC
I
VEE
V
CC
V
EE
P
D
PSRR
VCC
PSRR
VEE
R
HYS
= 23.5 kΩ
R
HYS
= 9.0 kΩ
Referred to AGND
@ +5.0 V
@ −5.2 V
Dual
Dual
Dual, without load
Dual, with load
2
10
4.75
−4.96
90
150
3.2
19
5.0
−5.2
120
180
85
85
20
70
−1
3
5
25
5.25
−5.45
150
230
Max
Unit
MHz
MHz
ps
ps
ps
mA
mA
V
V
mW
mW
dB
dB
mV
mV
V
kΩ
Equivalent input rise time bandwidth assumes a first-order input response and is calculated by the following formula: BW
EQ
= 0.22/√(tr
COMP2
– tr
IN2
), where tr
IN
is the
20/80 input transition time applied to the comparator and tr
COMP
is the effective transition time, as digitized by the comparator input.
Rev. D | Page 4 of 15
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltages
Positive Supply Voltage (V
CC
to GND)
Negative Supply Voltage (V
EE
to GND)
Ground Voltage Differential
Input Voltages
Input Common-Mode Voltage
Differential Input Voltage
Input Voltage, Latch Controls
Output
Output Current
Temperature
Operating Temperature, Ambient
Operating Temperature, Junction
Storage Temperature Range
Rating
−0.5 V to +6.0 V
−6.0 V to +0.5 V
−0.5 V to +0.5 V
−3.0 V to +4.0 V
−7.0 V to +7.0 V
V
EE
to +0.5 V
30 mA
−40°C to +85°C
125°C
−65°C to +150°C
ADCMP563/ADCMP564
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL CONSIDERATIONS
The
ADCMP563
QSOP 16-lead package option has a θ
JA
(junction-to-ambient thermal resistance) of 104°C/W in
still air.
The
ADCMP563
LFCSP 16-lead package option has a θ
JA
(junction-to-ambient thermal resistance) of 70°C/W in
still air.
The
ADCMP564
QSOP 20-lead package option has a θ
JA
(junction-to-ambient thermal resistance) of 80°C/W in
still air.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. D | Page 5 of 15
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