Si8660/61/62/63
L
O W
P
O W E R
S
I X
- C
HANNEL
D
IGITA L
I
SOLATOR
Features
High-speed operation
DC to 150 Mbps
No start-up initialization required
Wide Operating Supply Voltage
2.5–5.5 V
Up to 5000 V
RMS
isolation
60-year life at rated working voltage
High electromagnetic immunity
Ultra low power (typical)
5 V Operation
1.6 mA per channel at 1 Mbps
5.5 mA per channel at 100 Mbps
2.5 V Operation
1.5 mA per channel at 1 Mbps
3.5 mA per channel at 100 Mbps
Schmitt trigger inputs
Selectable fail-safe mode
Default high or low output
(ordering option)
Precise timing (typical)
10 ns propagation delay
1.5 ns pulse width distortion
0.5 ns channel-channel skew
2 ns propagation delay skew
5 ns minimum pulse width
Transient Immunity 50 kV/µs
AEC-Q100 qualification
Wide temperature range
–40 to 125 °C
RoHS-compliant packages
SOIC-16 wide body
SOIC-16 narrow body
Applications
Industrial automation systems
Medical electronics
Hybrid electric vehicles
Isolated switch mode supplies
Isolated ADC, DAC
Motor control
Power inverters
Communication systems
Ordering Information:
See page 26.
Safety Regulatory Approvals
UL 1577 recognized
Up to 5000 V
RMS
for 1 minute
CSA component notice 5A approval
IEC 60950-1, 61010-1, 60601-1
(reinforced
insulation)
VDE certification conformity
IEC 60747-5-2
(VDE0884 Part 2)
EN60950-1
(reinforced insulation)
Description
Silicon Lab's family of ultra-low-power digital isolators are CMOS devices
offering substantial data rate, propagation delay, power, size, reliability, and
external BOM advantages over legacy isolation technologies. The operating
parameters of these products remain stable across wide temperature ranges
and throughout device service life for ease of design and highly uniform
performance. All device versions have Schmitt trigger inputs for high noise
immunity and only require VDD bypass capacitors.
Data rates up to 150 Mbps are supported, and all devices achieve propagation
delays of less than 10 ns. Ordering options include a choice of isolation ratings
(3.75 and 5 kV) and a selectable fail-safe operating mode to control the default
output state during power loss. All products >1 kV
RMS
are safety certified by
UL, CSA, and VDE, and products in wide-body packages support reinforced
insulation withstanding up to 5 kV
RMS
.
Rev. 1.3 3/12
Copyright © 2012 by Silicon Laboratories
Si8660/61/62/63
Si8660/61/62/63
2
Rev. 1.3
Si8660/61/62/63
T
ABLE O F
C
ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.2. Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.4. Fail-Safe Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7. Land Pattern: 16-Pin Wide-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10.1. Si866x Top Marking (16-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10.2. Top Marking Explanation (16-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . 33
10.3. Si866x Top Marking (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.4. Top Marking Explanation (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . 34
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Rev. 1.3
3
Si8660/61/62/63
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Operating Temperature*
Supply Voltage
Symbol
T
A
V
DD1
V
DD2
Test Condition
150 Mbps, 15 pF, 5 V
Min
–40
2.5
2.5
Typ
25
—
—
Max
125
5.5
5.5
Unit
°C
V
V
*Note:
The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels,
and supply voltage.
Table 2. Electrical Characteristics
(V
DD1
= 5 V ±10%, V
DD2
= 5 V ±10%, T
A
= –40 to 125 ºC)
Parameter
VDD Undervoltage Threshold
VDD Undervoltage Threshold
VDD Negative-Going
Lockout Hysteresis
Positive-Going Input Threshold
Negative-Going
Input Threshold
Input Hysteresis
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Output Impedance
1
Symbol
VDDUV+
VDDUV–
VDD
HYS
VT+
VT–
V
HYS
V
IH
V
IL
V
OH
V
OL
I
L
Z
O
Test Condition
V
DD1
, V
DD2
rising
V
DD1
, V
DD2
falling
Min
1.95
1.88
50
Typ
2.24
2.16
70
1.67
1.23
0.44
—
—
4.8
0.2
—
50
Max
2.375
2.325
95
1.9
1.4
0.50
—
0.8
—
0.4
±10
—
Unit
V
V
mV
V
V
V
V
V
V
V
µA
All inputs rising
All inputs falling
1.4
1.0
0.38
2.0
—
loh = –4 mA
lol = 4 mA
V
DD1
,V
DD2
– 0.4
—
—
—
Notes:
1.
The nominal output impedance of an isolator driver channel is approximately 50
,
±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2.
t
PSK(P-P)
is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3.
Start-up time is the time period from the application of power to valid data at the output.
4
Rev. 1.3
Si8660/61/62/63
Table 2. Electrical Characteristics (Continued)
(V
DD1
= 5 V ±10%, V
DD2
= 5 V ±10%, T
A
= –40 to 125 ºC)
Parameter
Si8660Bx, Ex
V
DD1
V
DD2
V
DD1
V
DD2
Si8661Bx, Ex
V
DD1
V
DD2
V
DD1
V
DD2
Si8662Bx, Ex
V
DD1
V
DD2
V
DD1
V
DD2
Si8663Bx, Ex
V
DD1
V
DD2
V
DD1
V
DD2
Si8660Bx, Ex
V
DD1
V
DD2
Si8661Bx, Ex
V
DD1
V
DD2
Si8662Bx, Ex
V
DD1
V
DD2
Si8663Bx, Ex
V
DD1
V
DD2
Symbol
Test Condition
Min
Typ
Max
Unit
DC Supply Current
(All inputs 0 V or at Supply)
V
I
= 0(Bx), 1(Ex)
V
I
= 0(Bx), 1(Ex)
V
I
= 1(Bx), 0(Ex)
V
I
= 1(Bx), 0(Ex)
V
I
= 0(Bx), 1(Ex)
V
I
= 0(Bx), 1(Ex)
V
I
= 1(Bx), 0(Ex)
V
I
= 1(Bx), 0(Ex)
V
I
= 0(Bx), 1(Ex)
V
I
= 0(Bx), 1(Ex)
V
I
= 1(Bx), 0(Ex)
V
I
= 1(Bx), 0(Ex)
V
I
= 0(Bx), 1(Ex)
V
I
= 0(Bx), 1(Ex)
V
I
= 1(Bx), 0(Ex)
V
I
= 1(Bx), 0(Ex)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.2
3.5
8.8
3.7
1.7
3.4
7.9
4.8
2.2
3.0
7.5
5.6
2.6
2.6
6.5
6.5
1.9
5.3
12.3
5.6
2.7
5.1
11.1
7.2
3.3
4.5
10.5
8.4
3.9
3.9
9.1
9.1
mA
mA
mA
mA
1 Mbps Supply Current
(All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
—
—
—
—
—
—
—
—
5.0
4.2
4.9
4.6
5.1
4.7
4.9
4.9
7.0
5.9
6.9
6.4
7.1
6.6
6.8
6.8
mA
mA
mA
mA
Notes:
1.
The nominal output impedance of an isolator driver channel is approximately 50
,
±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2.
t
PSK(P-P)
is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3.
Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.3
5
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