NCP1239
Fixed Frequency
Current‐Mode Controller for
Flyback Converter
The NCP1239 is a fixed-frequency current-mode controller
featuring a high-voltage start-up current source to provide a quick and
lossless power-on sequence. This function greatly simplifies the
design of the auxiliary supply and the V
CC
capacitor by activating the
internal start-up current source to supply the controller during start-up,
transients, latch, stand-by etc.
With a supply range up to 35 V, the controller hosts a jittered 65 or
100-kHz switching circuitry operated in peak current mode control.
When the power on the secondary side starts to decrease, the controller
automatically folds back its switching frequency down to minimum
level of 26 kHz. As the power further goes down, the part enters skip
cycle while limiting the peak current that insures excellent efficiency
in light load condition.
NCP1239 features a timer-based fault detection circuitry that
ensures a quasi-flat overload detection, independent of the input
voltage.
Features
www.onsemi.com
SOIC−7
CASE 751U
PIN CONNECTIONS
Fault
FB
CS
GND
1
8
HV
2
3
6
VCC
DRV
4
5
•
Fixed-Frequency 65-kHz or 100-kHz Current-Mode Control
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Operation
Frequency Foldback Down to 26 kHz and Skip Mode to
Maximize Performance in Light Load Conditions
Adjustable Over Power Protection (OPP) Circuit
High-Voltage Current Source with Brown-Out (BO) Detection
Internal Slope Compensation
Internal Fixed Soft-Start
Frequency Jittering in Normal and Frequency Foldback Modes
64-ms Timer-Based Short-Circuit Protection with Auto-Recovery
or Latched Operation
Pre-Short Ready for Latched OCP Versions
Latched OVP on VCC (NCP1239 A, B, D, F or G Versions) –
Autorecovery for C and E Versions
Latched OVP/OTP Input for Improved Robustness
35-V V
CC
Operation
±500
mA Peak Source/Sink Drive Capability
Internal Thermal Shutdown
Extremely Low No-Load Standby Power
Pin-to-Pin Compatible with the Existing NCP1236/1247 Series
These Devices are Pb-Free and are RoHS Compliant
MARKING DIAGRAM
8
1239xfff
ALYWX
G
1
1239xfff = Specific Device Code
x = A, B, C, D, E, F or G
fff = 065 or 100
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information on page 24 of
this data sheet.
Typical Applications
•
AC-DC Converters for TVs, Set-Top Boxes and Printers
•
Offline Adapters for Notebooks and Netbooks
©
Semiconductor Components Industries, LLC, 2016
1
May, 2016 − Rev. 10
Publication Order Number
NCP1239/D
NCP1239
Vbulk
Vout
.
OVP
.
NCP1239
.
1
2
3
4
8
6
5
NTC
OPP
adjsut.
Figure 1. Application Schematic (OPP Adjustment)
Table 1. PIN FUNCTION DESCRIPTION
Pin No.
1
Pin Name
Fault
Description
The controller enters fault mode if the voltage of this pin is pulled above or below the fault thresholds.
A precise pull up current source allows direct interface with an NTC thermistor. Fault detection
triggers a latch.
Hooking an optocoupler collector to this pin will allow regulation.
This pin monitors the primary peak current but also offers an overpower compensation adjustment.
When the CS pin is brought above 1.2 V, the part is permanently latched off.
The controller ground.
The driver’s output to an external MOSFET gate.
This pin is connected to an external auxiliary voltage. An OVP comparator monitors this pin and
offers a means to latch the converter in fault conditions.
Non-connected for improved creepage distance.
Connected to the bulk capacitor or rectified ac line, this pin powers the internal current source to
deliver a start-up current. It is also used to provide the brown-out detection and the HV sensing for
the Overpower protection.
2
3
4
5
6
7
8
FB
CS
GND
DRV
VCC
NC
HV
Table 2. DEVICE OPTION AND DESIGNATIONS
Device
NCP1239AD065R2G
NCP1239BD065R2G
NCP1239CD065R2G
NCP1239DD065R2G
NCP1239ED065R2G
NCP1239FD065R2G
NCP1239AD100R2G
NCP1239BD100R2G
NCP1239GD100R2G
Frequency
65 kHz
65 kHz
65 kHz
65 kHz
65 kHz
65 kHz
100 kHz
100 kHz
100 kHz
OCP Protec-
tion
Latch
Auto−Recovery
Auto−Recovery
Auto−Recovery
Auto−Recovery
Latch
Latch
Auto−Recovery
Latch
V
cc
OVP
Threshold
25.5 V
25.5 V
25.5 V
25.5 V
25.5 V
32 V
25.5 V
25.5 V
25.5 V
V
cc
OVP
Protection
Latch
Latch
Auto−Recovery
Latch
Auto−Recovery
Latch
Latch
Latch
Latch
Fault Pin
Protection
Latch
Latch
Latch
Latch
Auto−Recovery
Latch
Latch
Latch
Latch
BO Levels
110 / 101
110 / 101
110 / 101
101 / 95
110 / 101
229 / 176
110 / 101
110 / 101
95 / 86
BO Timer
68 ms
68 ms
68 ms
68 ms
68 ms
68 ms
68 ms
68 ms
136 ms
www.onsemi.com
2
NCP1239
NC
VFault(OVP)
600−ns time
constant
Vdd
Clock
IOTP
Fault
Up counter
RST
OVP/OTP
gone?
HV sample
BO
BO end
HV detection
& sampling
HV
Vfault(clamp)
VFault(OTP)
Option for
OVP_VCC
4
BO
TSD
TSD
Dual HV startup
current source
Vcc(reset)
S
Q
Q
Vcc(reset)
Vdd
Skip
Jitter
TSD end
Rup
Vskip
Stop
Latch
Vdd
UVLO
Vcc logic
management
R
OVP_VCC
20us time
constant
VCC(OVP)
Vcc
Clock
BO end
FB
Foldback
Oscillator
65 kHz / 100 kHz
/4
+
Slope
Compensation
Clamp
S
PWM
HV sample
Soft−start
Ramp
8 ms
Soft−start
BO
SS end
OPP Current
Generation
Overcurrent
S
OCP_flag
Q
Q
Vdd
Ibias
Q
Q
Drv
R
GND
Latch
TSD
Iopp
VLimit1
LEB
300 ns
Skip
R
PWM
CS
LEB
120 ns
Up counter
4
RST
OVP_VCC
(option)
Protection
Mode
Reset
VLimit2
OCP_flag
Dmax
OCP
Timer
64 ms
OCP Fault
gone?
UVLO
Auto−recovery
Timer
1s
Vcc(reset)
Figure 2. Simplified Block Diagram
www.onsemi.com
3
NCP1239
Table 3. MAXIMUM RATINGS
Rating
Power Supply Voltage, V
CC
Pin, Continuous Voltage
Maximum Voltage on Low Power Pins CS, FB and Fault
Maximum Voltage on DRV Pin
High Voltage Pin
Thermal Resistance Junction-to-Air
Single Layer PCB 25 mm@, 2 Oz Cu Printed Circuit Copper Clad
Maximum Junction Temperature
Storage Temperature Range
ESD Capability (Note 2)
Human Body Model – All Pins Except HV
Machine Model
Charged-Device Model ESD Capability per JEDEC JESD22−C101E
Moisture Sensitivity Level
MSL
V
DRV
HV
R
θJ−A
T
J(max)
TSTG
ESD
HBM
ESD
MM
Symbol
V
CC
Value
−0.3 to 35
−0.3 to 5.5
−0.3 to 20
−0.3 to 650
250
150
−60 to 150
4
200
1
1
Unit
V
V
V
V
°C/W
°C
°C
kV
V
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per JEDEC JESD22−A114F
ESD Machine Model tested per JEDEC JESD22−A115C
Charged-Device Model ESD Capability tested per JEDEC JESD22−C101E
Latch-up Current Maximum Rating:
≤
150 mA per JEDEC standard: JESD78
Table 4. ELECTRICAL CHARACTERISTICS
(For typical values T
J
= 25°C, for min/max Values T
J
= −40°C to +125°C, V
HV
= 125 V, V
CC
= 11 V unless otherwise noted)
Parameter
START-UP SECTION
Minimum Voltage for Current Source Operation I
HV
= 90% I
START2
,
V
CC
= V
CC(on)
− 0.5 V
Current Flowing Out of V
CC
Pin
Current Flowing Out of V
CC
Pin
HV Pin Leakage Current
SUPPLY SECTION
Start-Up Threshold
HV Current Source Stop Threshold
HV Current Source Restart Threshold
Minimum Operating Voltage
Operating Hysteresis
V
CC
Level for I
START1
to I
START2
Transition
V
CC
Level where Logic Functions are Reset
Internal IC Consumption
Internal IC Consumption
Internal IC Consumption
V
CC
Decreasing
V
FB
= 3.2 V, F
SW
= 65 kHz
and C
L
= 0
V
FB
= 3.2 V, F
SW
= 65 kHz
and C
L
= 1 nF
V
FB
= 3.2 V, F
SW
= 100 kHz
and C
L
= 0
V
CC
Increasing
V
CC
Decreasing
V
CC
Decreasing
V
CC(on)
= V
CC(off)
V
CC(on)
V
CC(min)
V
CC(off)
V
CC(hys)
V
CC(inhibit)
V
CC(reset)
ICC1
ICC2
ICC1
11.0
9.0
8.0
3.0
0.7
6.5
−
−
−
12.0
10.0
8.8
−
1.2
7
1.4
2.1
1.7
13.0
11.0
9.4
−
1.7
7.5
2.2
3.0
2.5
V
V
V
V
V
V
mA
mA
mA
V
CC
= 0 V
V
CC
= V
CC(on)
– 0.5 V
V
HV
= 325 V
V
HV(min)
I
START1
I
START2
I
LEAK1
−
0.2
1.5
−
25
0.5
3
8
60
0.8
4.5
20
V
mA
mA
mA
Test Conditions
Symbol
Min
Typ
Max
Unit
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Guaranteed by design
2. CS pin source current is a sum of I
BIAS
and I
OPP
, thus at V
HV
= 125 V is observed the I
BIAS
only, because I
OPC
is switched off.
www.onsemi.com
4
NCP1239
Table 4. ELECTRICAL CHARACTERISTICS
(continued)
(For typical values T
J
= 25°C, for min/max Values T
J
= −40°C to +125°C, V
HV
= 125 V, V
CC
= 11 V unless otherwise noted)
Parameter
SUPPLY SECTION
Internal IC Consumption
Internal IC Consumption in Skip Cycle
Internal IC Consumption in Fault Mode
Internal IC Consumption before Start-Up
Internal IC Consumption before Start-Up
DRIVE OUTPUT
Rise Time (10−90%)
V
DRV
from 10 to 90%
V
CC
= V
CC(off)
+ 0.2 V,
C
L
= 1 nF
V
DRV
from 90 to 10%
V
CC
= V
CC(off)
+ 0.2 V,
C
L
= 1 nF
t
R
−
40
−
ns
V
FB
= 3.2 V, F
SW
= 100 kHz
and C
L
= 1 nF
V
CC
= 12 V, V
FB
= 0.775 V
Driving 8 A/650 V MOSFET
Fault or Latch
V
CC(min)
< V
CC
< V
CC(on)
V
CC
< V
CC(min)
ICC2
ICC(stb)
ICC3
ICC4
ICC5
−
−
−
−
−
3.1
500
400
310
20
4.0
−
−
−
−
mA
mA
mA
mA
mA
Test Conditions
Symbol
Min
Typ
Max
Unit
Fall Time (90−10%)
t
F
−
30
−
ns
Source Resistance
Sink Resistance
Peak Source Current
DRV High State,
V
DRV
= 0 V (Note 1)
V
CC
= V
CC(off)
+ 0.2 V,
C
L
= 1 nF
DRV Low State,
V
DRV
= V
CC
(Note 1)
V
CC
= V
CC(off)
+ 0.2 V,
C
L
= 1 nF
V
CC
= 9 V, R
DRV
= 33 kW
DRV High State
V
CC
= V
CC(OVP)
– 0.2 V,
DRV High State and Unloaded
R
OH
R
OL
I
SOURCE
−
−
−
6
6
500
−
−
−
W
W
mA
Peak Sink Current
I
SINK
−
500
−
mA
High State Voltage
(Low V
CC
Level)
High State Voltage
(High V
CC
Level)
CURRENT COMPARATOR
Input Pull-Up Current
Maximum Internal Current Setpoint
Abnormal Over-Current Fault Threshold
Default Internal Voltage Set Point for
Frequency Foldback Trip Point
Internal Peak Current Setpoint Freeze
Propagation Delay from V
LIMIT
Detection to
Gate Off-State
Leading Edge Blanking Duration
Abnormal Over-Current Fault Blanking
Duration for V
LIMIT3
Number of Clock Cycles before Fault
Confirmation
V
DRV(low)
V
DRV(clamp)
8.8
11.0
−
13.5
−
16.0
V
V
V
CS
= 0.7 V
T
J
from −40°C to +125°C
(No OPP)
T
J
= +25°C (No OPP)
~59% of V
LIMIT
~31% of V
LIMIT
DRV Output Unloaded
I
BIAS
V
LIMIT1
V
LIMIT2
V
FOLD(CS)
V
FREEZE(CS)
t
DEL
t
LEB1
t
LEB2
t
COUNT
−
0.752
1.10
−
−
−
−
−
−
1
0.800
1.20
475
250
50
300
120
4
−
0.848
1.30
−
−
100
−
−
−
mA
V
V
mV
mV
ns
ns
ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Guaranteed by design
2. CS pin source current is a sum of I
BIAS
and I
OPP
, thus at V
HV
= 125 V is observed the I
BIAS
only, because I
OPC
is switched off.
www.onsemi.com
5
京公网安备 11010802033920号
EEWORLD
