7c1006: 11-25-91
Revision: April 10, 1995
ADVANCED INFORMATION
CMOS static RAM organized as 262,144
words by 4 bits. Easy memory expansion is
D
provided by an active LOW chip enable
(CE), an active LOW output enable (OE),
and three state drivers. The device has an
D
automatic power down feature that signifi
D
cantly reduces power consumption when
D
deselected.
D
Writing to the device is accomplished by
taking chip enable (CE) and write enable
(WE) inputs LOW. Data on the four I/O
D
pins (I/O
0
through I/O
3
) is then written
Functional Description
into the location specified on the address
The CY7C1016 is a high performance pins (A
0
through A
17
).
Features
High speed
t
AA
= 10 ns
Output enable (OE) feature
CMOS for optimum speed/power
Center power/ground pinout
Automatic power down when
deselected
TTL compatible inputs and outputs
CY7C1016
256K x 4 Static RAM
Reading from the device is accomplished
by taking chip enable (CE) LOW while
forcing write enable (WE) HIGH. Under
these conditions, the contents of the
memory location specified by the address
pins will appear on the four I/O pins.
The four input/output pins (I/O
0
through
I/O
3
) are placed in a high impedance state
when the device is deselected (CE HIGH),
or during a write operation (CE and WE
LOW).
The CY7C1016 is available in standard
400 mil wide SOJs.
Logic Block Diagram
Pin Configuration
SOJ
Top View
NC
A
0
A
1
A
2
A
3
CE
I/O
0
INPUT BUFFER
A
1
SENSE AMPS
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
ROW DECODER
I/O
3
V
CC
GND
I/O
1
WE
A
4
A
5
I/O
2
A6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
17
A
16
A
15
A
14
A
13
OE
I/O
3
GND
V
CC
I/O
2
A
12
A
11
A
10
A
9
A
8
NC
512 x 512 x 4
ARRAY
A
7
NC
I/O
1
C1016-2
I/O
0
COLUMN
DECODER
POWER
DOWN
CE
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
0
WE
C1016-1
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
Document #: 38-00439
Cypress Semiconductor Corporation
7C1016-10
Commercial
Military
Commercial
Military
D
10
175
55
7C1016-12
12
165
175
50
50
7C1016-15
15
155
165
40
40
3901 North First Street
1
D
San Jose
D
CA 95134
D
408-943-2600
April 1995
FPGA/CPLD
京公网安备 11010802033920号
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