CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T
J
= T
C
= T
A
DC Electrical Specifications
PARAMETER
V+
V-
G_0
G_m
G_f
DG_m0
DG_f0
DG_fm
V
IN
V
OUT
I
B
R
IN
V
OS_0
V
OS_M
V
OS_F
Z
OUT
V
SA
+ = V
A
+ = +5V, V
SA
- = V
A
- = -5V, T
A
= +25°C, exposed die plate = -5V, unless otherwise specified.
CONDITION
MIN
+4.5
-4.5
X2 = 5V, 150Ω load
1.81
1.66
1.52
-7.5
-13.5
-10.0
Gain falls to 90% of nominal
X2 = +5V into 150Ω load
-0.7
-5
1
10
X2 = +5V, 75 + 75Ω load
-200
-200
-200
Chip enable = +5V
Chip enable = 0V
4.5
-150
-140
-130
4.8
1
-38
-53
75
-10.5
-13
10
87
-8.6
-11.6
11.8
0.9
1.6
30
1.25
0.8
1.15
1.6
115
-7
-10
15.5
mA
mA
mA
V
V
60
60
60
5.1
1.89
1.84
1.79
-2.5
-6.0
-2.6
TYP
MAX
+5.5
-5.5
2.04
2.04
2.04
2.5
2.5
4.0
1.3
1.6
5
%
%
%
V
V
µA
MΩ
mV
mV
mV
Ω
MΩ
dB
dB
mA
mA
mA
UNIT
V
V
DESCRIPTION
Positive Supply Range
Negative Supply Range
Gain Zero Delay
Gain Mid Delay
Gain Full Delay
Difference in Gain, 0 to Mid
Difference in Gain, 0 to Full
Difference in Gain, Mid to Full
Input Voltage Range
Output Voltage Range
Input Bias Current
Input Resistance
Output Offset 0 Delay
Output Offset Full Delay
Output Offset Mid Delay
Output Impedance
+PSRR
-PSRR
I
SP
I
SM
I
SMO
I
SPO
Δ
I
SP
Rejection of Positive Supply
Rejection of Negative Supply
Supply Current (Note 1)
Supply Current (Note 1)
Supply Current (Note 1)
Supply Current (Note 1)
Supply Current (Note 1)
Supply Current (Note 1)
Output Drive Current
Logic High
Logic Low
X2 = +5V into 75 + 75Ω load
X2 = +5V into 75 + 75Ω load
Chip enable = +5V current on V
SP
Chip enable = +5V current in V
SM
Chip enable = +5V current in V
SMO
Chip enable = +5V current in V
SPO
Increase in I
SP
per unit step in delay
Chip enable = 0V current in V
SP
10Ω load, 0.5V drive, X2 = 5V
Switch high threshold
Switch low threshold
I
SP OFF
I
OUT
L
HI
L
LO
NOTE:
1. All supply currents measured with Delay R = 0ns, G = mid delay, B = full delay.
2
FN7441.4
February 8, 2008
EL9115
AC Electrical Specifications
PARAMETER
BW -3dB
BW 0.1dB
SR
t
R
- t
F
V
OVER
Glitch
THD
X
t
V
N
d
t
t
MAX
D
ELDT
t
PD
t
MAX
t_en_ck
3dB Bandwidth
0.1dB Bandwidth
Slew Rate
Transient Response Time
Voltage Overshoot
Switching Glitch
Total Harmonic Distortion
Hostile Crosstalk
Output Noise
Delay Increment
Maximum Delay
Delay Diff Between Channels
Propagation Delay
Max s_clock Frequency
Minimum Separation Between Serial
Enable and Clock
Measured input to output
Maximum programming clock speed
Check enable low edge can occur after
t_en_ck of previous (ignored) clock and up to
before t_en_ck of next (wanted) clock. Clock
edges occurring within t_en_ck of the enable
edge will have uncertain effect.
10
8.5
V
SA
+ = V
A
+ = +5V, V
SA
- = V
A
- = -5V, T
A
= +25°C, exposed die plate = -5V, unless otherwise specified.
CONDITION
0ns Delay Time
0ns Delay Time
0ns Delay Time
20% to 80%, for all delays, 1V step
for any delay, response to 1V step input
Time for o/p to settle after last s_clock edge
1V
P-P
10MHz sinewave, offset by +0.2V at
mid delay setting
Stimulate G, measure R/B at 1MHz
Gain X2, measured at 75Ω load
1.75
55
MIN
TYP
122
60
400
2.5
5
100
-50
-80
2.5
2
62
1.6
9.8
11
10
2.25
70
-40
10
MAX
UNIT
MHz
MHz
V/µs
ns
%
ns
dB
dB
mV
RMS
ns
ns
%
ns
MHz
ns
DESCRIPTION
Pin Descriptions
PIN NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Thermal Pad
PIN NAME
VSP
RIN
GND
GIN
VSM
BIN
CENABLE
NSENABLE
SDATA
SCLOCK
BOUT
VSMO
GOUT
GNDO
ROUT
VSPO
TESTB
TESTG
TESTR
X2
PIN DESCRIPTION
+5V for delay circuitry and input amp
Red channel input, ref GND
0V for delay circuitry supply
Green channel input, ref GND
-5V for input amp
Blue channel input, ref GND
Chip enable logical +5V enables chip
ENABLE for serial input; enable on low
Data into registers; logic threshold 1.2V
Clock to enter data; logical; data written on negative edge
Blue channel output, ref GND
O
-5V for output buffers
Green channel output, ref GND
O
0V reference for input and output buffers
Red channel output, ref GND
O
+5V for output buffers
Blue channel phase detector output
Green channel phase detector output
Red channel phase detector output
Sets gain to 2X if input high; X1 otherwise
Must be connected to -5V
3
FN7441.4
February 8, 2008
EL9115
Typical Performance Curves
Delay = 0ns
-3dB@122MHz
Delay = 0ns
Delay = 62ns
Delay = 62ns
-3dB@80MHz
Delay 10, 20, 30, 40 and 50ns
Delay 10, 20, 30, 40 and 50ns
FIGURE 1. GAIN vs FREQUENCY
FIGURE 2. GAIN vs FREQUENCY
DELAY TIME (ns)
DELAY TIME (ns)
DELAY
FIGURE 3. TYPICAL DC OFFSET vs DELAY TIME (X2 = Hi)
FIGURE 4. TYPICAL DC OFFSET vs DELAY TIME (X2 = Low)
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