CAT9555
16-bit I
2
C and SMBus I/O Port with Interrupt
FEATURES
s
400kHz I
2
C bus compatible*
s
2.3V to 5.5V operation
s
Low stand-by current
s
5V tolerant I/Os
s
16 I/O pins that default to inputs at power-up
s
High drive capability
s
Individual I/O configuration
s
Polarity inversion register
s
Active low interrupt output
s
Internal power-on reset
s
No glitch on power-up
s
Noise filter on SDA/SCL inputs
s
Cascadable up to 8 devices
s
Industrial temperature range
s
RoHS-compliant 24-lead SOIC and TSSOP, and
DESCRIPTION
The CAT9555 is a CMOS device that provides 16-bit
parallel input/output port expansion for I
2
C and SMBus
compatible applications. These I/O expanders provide
a simple solution in applications where additional I/Os
are needed: sensors, power switches, LEDs,
pushbuttons, and fans.
The CAT9555 consists of two 8-bit Configuration ports
(input or output), Input, Output and Polarity inversion
registers, and an I
2
C/SMBus-compatible serial interface.
Any of the sixteen I/Os can be configured as an input or
output by writing to the configuration register. The system
master can invert the CAT9555 input data by writing to
the active-high polarity inversion register.
The CAT9555 features an active low interrupt output
which indicates to the system master that an input state
has changed.
The three address input pins provide the device's
extended addressing capability and allow up to eight
devices to share the same bus. The fixed part of the I
2
C
slave address is the same as the CAT9554, allowing up
to eight of these devices in any combination to be
connected on the same bus.
24-pad TQFN (4 x 4 mm) packages
APPLICATIONS
s
White goods (dishwashers, washing machines)
s
Handheld devices (cell phones, PDAs, digital
cameras)
s
Data Communications (routers, hubs and
servers)
For Ordering Information details, see page 16.
BLOCK DIAGRAM
A0
A1
A2
8-BIT
INPUT/
OUTPUT
PORTS
I/O1.0
I/O1.1
I/O1.2
I/O1.3
I/O1.4
I/O1.5
I/O1.6
I/O1.7
I2C/SMBUS
CONTROL
I/O0.0
I/O0.1
SCL
SDA
INPUT
FILTER
8-BIT
INPUT/
OUTPUT
PORTS
I/O0.2
I/O0.3
I/O0.4
I/O0.5
I/O0.6
I/O0.7
POWER-ON
RESET
VINT
LP FILTER
WRITE pulse
READ pulse
WRITE pulse
READ pulse
VCC
VCC
~
INT
NOTE: ALL I/Os ARE SET TO INPUTS AT RESET
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I
2
C Bus Protocol.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. MD-9003, Rev. G
CAT9555
PIN CONFIGURATION
SOIC (W) / TSSOP (Y)
24 A2
INT
A1
A2
I/O0.0
I/O0.1
I/O0.2
I/O0.3
I/O0.4
I/O0.5
I/O0.6
I/O0.7
VSS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
19
17
16
15
14
13
VCC
SDA
SCL
A0
I/O1.7
I/O1.6
I/O1.5
I/O1.4
I/O1.3
I/O1.2
I/O1.1
I/O1.0
TQFN (HV6)
21 VCC
20 SDA
19 SCL
22
INT
23 A1
I/O0.0 1
I/O0.1 2
I/O0.2 3
I/O0.3 4
I/O0.4 5
I/O0.5 6
I/O1.0 10
I/O1.2 12
I/O1.1 11
I/O0.6 7
I/O0.7 8
VSS 9
18 A0
17 I/O1.7
16 I/O1.6
15 I/O1.5
14 I/O1.4
13 I/O1.3
4 x 4 mm
Top View
PIN DESCRIPTION
SOIC / TSSOP
1
2
3
4-11
12
13-20
21
22
23
24
TQFN
22
23
24
1-8
9
10-17
18
19
20
21
PIN NAME
INT
A1
A2
I/O0.0 - I/O0.7
V
SS
I/O1.0 - I/O1.7
A0
SCL
SDA
V
CC
FUNCTION
Interrupt Output (open drain)
Address Input 1
Address Input 2
I/O Port 0.0 to I/O Port 0.7
Ground
I/O Port 1.0 to I/O Port 1.7
Address Input 0
Serial Clock
Serial Data
Power Supply
Doc. No. MD-9003 , Rev. G
2
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT9555
ABSOLUTE MAXIMUM RATINGS
(1)
V
CC
with Respect to Ground ............... –0.5V to +6.5V
Voltage on Any Pin with
Respect to Ground ........................ –0.5V to +5.5V
DC Current on I/O
0
to I/O
7 ...........................................
+50 mA
DC Input Current ............................................. +20 mA
V
CC
Supply Current .......................................... 160mA
V
SS
Supply Current .......................................... 200mA
Package Power Dissipation
Capability (T
A
= 25°C) ................................... 1.0W
Junction Temperature ..................................... +150°C
Storage Temperature ........................ -65°C to +150°C
RELIABILITY CHARACTERISTICS
Symbol
VZAP
(2)
ILTH
(2)
Parameter
ESD Susceptibility
Latch-up
Reference Test Method
JEDEC Standard JESD22
JEDEC JESD78A
Min
2000
100
Units
Volts
mA
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) This parameter is tested initially and after a design or process change that affects the parameter.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. MD-9003, Rev. G
CAT9555
D.C. OPERATING CHARACTERISTICS
V
CC
= 2.3 to 5.5 V; V
SS
= 0V; T
A
= -40°C to +85°C, unless otherwise specified
Symbol
Supplies
V
CC
I
CC
I
stbl
I
stbh
V
POR
Supply voltage
Supply current
Standby current
Standby current
Power-on reset voltage
Operating mode; V
CC
= 5.5 V; no load; f
SCL
= 100
kHz
Standby mode; V
CC
= 5.5 V; no load; V
I
= V
SS
;
f
SCL
= 0 kHz; I/O = inputs
Standby mode; V
CC
= 5.5 V; no load; V
I
= V
CC
;
f
SCL
= 0 kHz; I/O = inputs
No load; V
I
= V
CC
or VSS
2.3
—
—
—
—
—
135
1.1
0.75
1.5
5.5
200
1.5
1
1.65
V
µA
mA
µA
V
Parameter
Conditions
Min
Typ
Max
Unit
SCL, SDA, INT
V
IL
(1)
V
IH
(1)
I
OL
I
L
C
I
(2)
C
O
(2)
A0, A1, A2
V
IL
(1)
V
IH
(1)
I
LI
I/Os
V
IL
V
IH
I
OL
Low level input voltage
High level input voltage
Low level output current
V
OL
= 0.5 V; V
CC
= 2..3 V to 5.5 V (3)
V
OL
= 0.7 V; V
CC
= 2..3 V to 5.5 V (3)
I
OH
= – 8 mA; V
CC
= 2.3 V; (4)
I
OH
= – 10 mA; V
CC
= 2.3 V; (4)
I
OH
= – 8 mA; V
CC
= 3.0 V; (4)
V
OH
High level output voltage
I
OH
= – 10 mA; V
CC
= 3.0 V; (4)
I
OH
= – 8 mA; V
CC
= 4.75 V; (4)
I
OH
= – 10 mA; V
CC
= 4.75 V; (4)
I
IH
I
IL
C
I
(2)
C
O
(2)
Input leakage current
Input leakage current
Input capacitance
Output capacitance
V
CC
= 3.6 V; V
I
= V
CC
V
CC
= 5.5 V; V
I
= V
SS
2.5
4.1
4.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
-100
5
8
V
V
V
µA
µA
pF
pF
-0.5
0.7 V
CC
8
10
1.8
1.7
2.6
—
—
8 to 20
10 to 24
—
—
—
0.3 V
CC
5.5
—
—
—
—
—
V
V
mA
mA
V
V
V
Low level input voltage
High level input voltage
Input leakage current
-0.5
0.7 V
CC
-1
—
—
—
0.3 V
CC
5.5
1
V
V
µA
Low level input voltage
High level input voltage
Low level output current
Leakage current
Input capacitance
Output capacitance
V
OL
= 0.4V
V
I
= V
CC
= V
SS
V
I
= V
SS
V
O
= V
SS
-0.5
0.7 V
CC
3
– 1
—
—
—
—
—
—
—
—
0.3 V
CC
5.5
—
+1
6
8
V
V
mA
µA
pF
pF
Notes:
1. V
IL
min and V
IH
max are reference values only and are not tested.
2. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
3. Each I/Os must be externally limited to a maximum of 25 mA and each octal (I/O0.0 to I/O0.7 and I/O1.0 to I/O1.7) must be limited to a
maximum current of 100 mA for a device total of 200 mA.
4. The total current sourced by all I/Os must be limited to 160 mA.
Doc. No. MD-9003 , Rev. G
4
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT9555
A.C. CHARACTERISTICS
V
CC
= 2.3V to 5.5V, T
A
= -40°C to +85°C, unless otherwise specified (Note 1).
Symbol
f
SCL
t
SP
t
LOW
t
HIGH
t
R
t
F
(2)
Parameter
Clock Frequency
Input Filter Spike Suppression (SDA, SCL)
Clock Low Period
Clock High Period
SDA and SCL Rise Time
SDA and SCL Fall Time
Start Condition Hold Time
Start Condition Setup Time (for a Repeated Start)
Data Input Hold Time
Data In Setup Time
Stop Condition Setup Time
SCL Low to Data Out Valid
Data Out Hold Time
Time the Bus must be Free Before a New Transmission Can Start
Min
Max
400
50
Units
kHz
ns
µs
µs
1.3
0.6
20
20
0.6
0.6
0
100
0.6
900
50
1.3
300
300
ns
ns
µs
µs
ns
ns
µs
ns
ns
µs
(2)
t
HD:STA
t
SU:STA
t
HD:DAT
t
SU:DAT
t
SU:STO
t
AA
t
DH
t
BUF
(2)
Port Timing
t
PV
t
PS
t
PH
Output Data Valid
Input Data Setup Time
Input Data Hold Time
100
1
200
ns
ns
µs
Interrupt Timing
t
IV
t
IR
Interrupt Valid
Interrupt Reset
4
4
µs
µs
Notes:
1. Test conditions according to "AC Test Conditions" table.
2. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. MD-9003, Rev. G
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