P4C188/188L
P4C188/P4C188L
ULTRA HIGH SPEED 16K x 4
STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25 ns (Commercial)
– 12/15/20/25/35 (Industrial)
– 15/20/25/35/45 ns (Military)
Low Power (Commercial/Military)
– 715 mW Active – 12/15
– 550/660 mW Active – 20/25/35/45
– 193/220 mW Standby (TTL Input)
– 83/110 mW Standby (CMOS Input) P4C188
– 15 mW Standby (CMOS Input)
(P4C188L Military)
Single 5V
±
10% Power Supply
Data Retention with 2.0V Supply
(P4C188L Military)
Three-State Outputs
TTL/CMOS Compatible Outputs
Fully TTL Compatible Inputs
Standard Pinout (JEDEC Approved)
– 22-Pin 300 mil DIP
– 24-Pin 300 mil SOJ
– 22-Pin 290 x 490 mil LCC
DESCRIPTION
The P4C188 and P4C188L are 65,536-bit ultra high speed
static RAMs organized as 16K x 4. The CMOS memories
require no clocks or refreshing and have equal access and
cycle times. Inputs and outputs are fully TTL-compatible.
The RAMs operate from a single 5V±10% tolerance power
supply. With battery backup, data integrity is maintained for
supply voltages down to 2.0V. Current drain is typically 10
µA
from a 2.0V supply.
Access times as fast as 12 nanoseconds are available,
permitting greatly enhanced system speeds. CMOS is
utilized to reduce power consumption to a low 715mW
active, 193mW standby and only 5mW in the P4C188L
version.
The P4C188 and P4C188L are available in 22-pin 300 mil
DIP, 24-pin 300 mil SOJ and 22-pin LCC packages provid-
ing excellent board level densities.
FUNCTIONAL BLOCK DIAGRAM
A
(8)
A
I/O
1
I/O
2
I/O
3
I/O
4
ROW
SELECT
65,536-BIT
MEMORY
ARRAY
PIN CONFIGURATIONS
V
CC
22
1
A
0
A
1
A
2
A
3
A
4
A
5
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
V
CC
A
13
A
12
A
11
A
10
A
9
I/O
4
I/O
3
I/O
2
I/O
1
WE
A
2
A
3
A
4
A
5
A
6
A
7
A
8
2
3
4
5
6
7
8
9
10
11 12
A
13
21
20
19
18
17
16
15
14
13
A
1
A
0
A
12
A
11
A
10
A
9
I/O
4
I/O
3
I/O
2
INPUT
DATA
CONTROL
COLUMN I/O
A
6
A
7
A
8
CE
GND
GND
WE
COLUMN
SELECT
CE
A
(6)
WE
A
DIP (P3, D3)
TOP VIEW
LCC (L3)
TOP VIEW
For SOJ pin configuration, please see Selection Guide Page.
Means Quality, Service and Speed
1Q97
63
I/O
1
CE
P4C188/188L
MAXIMUM RATINGS
(1)
Symbol
V
CC
Parameter
Power Supply Pin with
Respect to GND
Terminal Voltage with
Respect to GND
(up to 7.0V)
Operating Temperature
Value
–0.5 to +7
–0.5 to
V
CC
+0.5
–55 to +125
Unit
V
Symbol
T
BIAS
T
STG
V
°C
P
T
I
OUT
Parameter
Temperature Under
Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
–55 to +125
–65 to +150
1.0
50
Unit
°C
°C
W
mA
V
TERM
T
A
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade(2)
Military
Ambient
Temperature
GND
0V
0V
0V
V
CC
5.0V
±
10%
5.0V
±
10%
5.0V
±
10%
CAPACITANCES
(4)
V
CC
= 5.0V, T
A
= 25°C, f = 1.0MHz
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Conditions Typ. Unit
V
IN
= 0V
5
7
pF
pF
–55°C to +125°C
–40°C to +85°C
Industrial
0°C to +70°C
Commercial
Output Capacitance V
OUT
= 0V
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage
(2)
Symbol
V
IH
V
IL
V
HC
V
LC
V
CD
V
OL
V
OH
I
LI
I
LO
I
SB
Parameter
Input High Voltage
Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
Input Clamp Diode Voltage V
CC
= Min., I
IN
= 18 mA
Output Low Voltage
(TTL Load)
Output High Voltage
(TTL Load)
Input Leakage Current
Output Leakage Current
I
OL
= +8 mA, V
CC
= Min.
I
OH
= –4 mA, V
CC
= Min.
V
CC
= Max.
V
IN
= GND to V
CC
V
CC
= Max.,
CE
= V
IH
,
V
OUT
= GND to V
CC
Mil.
Com’l.
Mil.
Com’l.
2.4
–10
–5
–10
–5
___
___
___
___
+10
+5
+10
+5
40
35
20
15
Test Conditions
P4C188
Min
Max
2.2
V
CC
+0.5
–0.5
(3)
–0.5
(3)
0.8
0.2
–1.2
0.4
2.4
–5
n/a
–5
n/a
___
___
___
___
+5
n/a
+5
n/a
40
n/a
2.7
n/a
P4C188L
Unit
Min
Max
2.2
V
CC
+0.5 V
–0.5
(3)
–0.5(3)
0.8
0.2
–1.2
0.4
V
V
V
V
V
V
µA
µA
mA
V
CC
–0.2 V
CC
+0.5 V
CC
–0.2 V
CC
+0.5
Standby Power Supply
CE
≥
V
IH
Mil.
Current (TTL Input Levels) V
CC
= Max .,
Ind./Com’l.
f = Max., Outputs Open
Standby Power Supply
Current
(CMOS Input Levels)
CE
≥
V
HC
Mil.
V
CC
= Max.,
Ind./Com’l.
f = 0, Outputs Open
V
IN
≤
V
LC
or V
IN
≥
V
HC
I
SB1
mA
n/a = Not Applicable
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
64
P4C188/188L
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol
Parameter
Temperature
Range
Commercial
I
CC
Dynamic Operating Current*
Industrial
Military
–10
180
N/A
N/A
–12
170
180
N/A
–15
160
170
170
–20
155
160
160
–25
150
155
155
–35
N/A
150
150
–45
N/A
N/A
145
Unit
mA
mA
mA
*V
CC
= 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V.
CE
= V
IL
DATA RETENTION CHARACTERISTICS (P4C188L Military Temperature Only)
Symbol
V
DR
I
CCDR
t
CDR
t
R†
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to
Data Retention Time
Operation Recovery Time
CE
≥
V
CC
–0.2V,
V
IN
≥
V
CC
–0.2V or
V
IN
≤
0.2V
Test Conditions
Min
2.0
10
0
t
RC§
15
600
900
Typ.*
V
CC
=
2.0V
3.0V
Max
V
CC
=
2.0V 3.0V
Unit
V
µA
ns
ns
*T
A
= +125°C
§
†
t
RC
= Read Cycle Time
This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
DATA RETENTION MODE
V
CC
t
CDR
CE
V
IH
V
DR
V
IH
4.5V
V
DR
≥
2V
4.5V
t
R
65
P4C188/188L
AC CHARACTERISTICS—READ CYCLE
(V
CC
= 5V
±
10%, All Temperature Ranges)
(2)
Sym.
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
t
PU
t
PD
Parameter
Read Cycle Time 10
Address Access
Time
Chip Enable
Access Time
Output Hold from
Address Change
Chip Enable to
Output in Low Z
Chip Disable to
Output in High Z
Chip Enable to
Power Up Time
Chip Disable to
Power Down
Time
0
2
2
-10
12
10
10
2
2
5
0
10
-12
15
12
12
2
2
6
0
12
-15
20
15
15
2
3
6
0
15
-20
-25
25
20
20
2
3
8
0
20
25
10
0
25
25
2
3
35
-35
45
35
35
2
3
20
0
35
-45
Unit
ns
45
45
ns
ns
ns
ns
25
ns
ns
45
ns
Min Max Min Max Min Max Min Max Min Max Min Max Min Max
TIMING WAVEFORM OF READ CYCLE NO. 1
(5)
(8)
t
RC
ADDRESS
t
AA
t
OH
DATA OUT
PREVIOUS DATA VALID
DATA VALID
TIMING WAVEFORM OF READ CYCLE NO. 2
(6)
t
RC
CE
(7)
t
AC
DATA VALID
t
HZ
(7)
t
LZ
DATA OUT
t
PU
V
CC
SUPPLY
CURRENT
I
CC
I
SB
HIGH IMPEDANCE
t
PD
Notes:
5.
CE
is LOW and
WE
is HIGH for READ cycle.
6.
WE
is HIGH, and address must be valid prior to or coincident with
CE
transition LOW.
7. Transition is measured
±200mV
from steady state voltage prior to
change with specified loading in Figure 1. This parameter is sampled
and not 100% tested.
8. Read Cycle Time is measured from the last valid address to the first
transitioning address.
66
P4C188/188L
AC CHARACTERISTICS - WRITE CYCLE
(V
CC
= 5V
±
10%, All Temperature Ranges)
(2)
Sym.
t
WC
t
CW
Parameter
Write Cycle Time
Chip Enable
Time to
End of Write
Address Valid
to End of Write
Address
Set-up Time
Write Pulse
Width
Address Hold
Time from
End of Write
Data Valid to
End of Write
Data Hold
Time
Write Enable
to Ourput in
High Z
Output Active
from End
of Write
2
-10
10
7
12
8
-12
13
10
-15
20
13
-20
25
15
-25
35
25
-35
45
35
-45
Min Max Min Max Min Max Min Max Min Max Min Max Min Max
Unit
ns
ns
t
AW
t
AS
t
WP
t
AH
7
0
8
0
8
0
9
0
10
0
10
0
15
0
13
0
20
0
15
0
25
0
25
0
35
0
35
0
ns
ns
ns
ns
t
DW
t
DH
t
WZ
5
0
5
6
0
6
7
0
6
8
0
8
10
0
10
15
0
15
20
5
20
ns
ns
ns
t
DW
2
2
2
2
3
3
ns
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)
(9)
WE
t
WC
ADDRESS
t
CW
CE
t
AW
t
WP
WE
t
AS
DATA IN
t
WZ
DATA OUT
DATA UNDEFINED
HIGH IMPEDANCE
(12)
(11)
t
WR
t
AH
t
DW
DATA VALID
t
DH
t
OW
(10, 12)
Notes:
9.
CE
and
WE
must be LOW for WRITE cycle.
10. If
CE
goes HIGH simultaneously with
WE
HIGH, the output remains
in a high impedance state.
11. Write Cycle Time is measured from the last valid address to the first
transition address.
12. Transition is measured
±200mV
from steady state voltage prior to
change with specified loading in Figure 1. This parameter is sampled
and not 100% tested.
67
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