L8C211/221/231/241
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Synchronous FIFO
L8C211/221/231/241
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Synchronous FIFO
DESCRIPTION
The
L8C211, L8C221, L8C231,
and
L8C241
are synchronous dual-port
First-In/First-Out (FIFO) memories.
The FIFO memory products are
organized as:
L8C211 — 512 x 9-bit
L8C221 — 1024 x 9-bit
L8C231 — 2048 x 9-bit
L8C241 — 4096 x 9-bit
The read and write operations are
internally sequential through the use
of ring pointers. No address informa-
tion is required to load and unload
data. Data present at the input port is
written to the FIFO if the Write Clock
is pulsed when the device is enabled
for writing. Data is read from the
FIFO if the Read Clock is pulsed when
the device is enabled for reading.
Multiple FIFOs can be connected
together to expand the word width
and depth.
These FIFOs are designed to have the
fastest data access possible. Even in
lower cycle time applications, faster
access time can eliminate timing
bottlenecks as well as leave enough
margin to allow the use of the devices
without external bus drivers.
FEATURES
u
First-In/First-Out (FIFO) using
Dual-Port Memory
u
Write and Read Clocks can be
synchronous or asynchronous
u
Advanced CMOS Technology
u
High Speed — to 15 ns Cycle Time
u
Empty and Full Warning Flags
u
Programmable Almost-Empty and
Almost-Full Warning Flags
u
Plug Compatible with IDT722x1
u
Package Styles Available:
• 32-pin Plastic LCC, J-Lead
1
2
3
4
5
6
7
8
L8C211/221/231/241 B
LOCK
D
IAGRAM
RS
RESET
LOGIC
WEN
1
WEN
2
WCLK
WRITE
CONTROL
O
9
1
LE
DATA INPUTS
D
8-0
9
INPUT
REGISTER
RAM ARRAY
512 x 9-bit
1K x 9-bit
2K x 9-bit
4K x 9-bit
OUTPUT
REGISTER
DATA OUTPUTS
Q
8-0
Each device utilizes a special algo-
rithm that loads and empties data on a
first-in/first-out basis. Full and
Empty Flags are provided to prevent
data overflow and underflow. Pro-
grammable Almost Full and Almost
Empty Flags are provided and may be
programmed to trigger at any position
in the memory array.
TE
OFFSET
REGISTER
FLAG
LOGIC
EF PAE FF PAF
LD
9
10
11
12
13
14
O
REN
1
REN
2
RCLK
OE
BS
WRITE
POINTER
READ
POINTER
READ
CONTROL
FIFO Products
03/04/99–LDS.8C211/21/31/41-C
L8C211/221/231/241
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Synchronous FIFO
WEN
1
— Write Enable 1
If the FIFO is configured to allow
loading of the offset registers, WEN
1
is
the only write enable. If WEN
1
is
LOW, data on D
8-0
is written to the
FIFO on the rising edge of WCLK. If
WEN
1
and LD are LOW, data on D
8-0
is written to the programmable offset
registers as defined in the WEN
2
/LD
section. If the FIFO is configured to
have two write enables, data on D
8-0
is
written to the FIFO on the rising edge
of WCLK if WEN
1
is LOW and WEN
2
is HIGH. When the FIFO is full,
WEN
1
is ignored except when loading
the offset registers.
WEN
2
/LD — Write Enable 2/Load
The function of this signal is defined
during reset. If during reset WEN
2
/
LD is HIGH, this signal functions as a
second write enable (WEN
2
). WEN
2
is
used when depth expansion is needed
(see Depth Expansion Mode Section).
If during reset WEN
2
/LD is LOW, this
signal functions as an offset register
load/read control. When WEN
2
/LD
is configured to be a write enable, data
on D
8-0
is written to the FIFO on the
rising edge of WCLK if WEN
1
is LOW
and WEN
2
is HIGH. When the FIFO
is full, WEN
2
is ignored.
SIGNAL DEFINITIONS
Power
V
CC
and GND
+5 V power supply. All pins must be
connected.
Clocks
WCLK — Write Clock
Data present on D
8-0
is written into
the FIFO on the rising edge of WCLK
when the FIFO is configured for
writing. The Full Flag (FF) and the
Programmable Almost-Full Flag (PAF)
are synchronized to the rising edge of
WCLK.
RCLK — Read Clock
Data is read from the FIFO and
presented on the output port (Q
8-0
)
after
t
D
has elapsed from the rising
edge of RCLK if the FIFO is config-
ured for reading and if the output port
is enabled. The Empty Flag (EF) and
the Programmable Almost-Empty Flag
(PAE) are synchronized to the rising
edge of RCLK. The Write and Read
Clocks can be tied together and driven
by the same external clock or they
may be controlled by seperate external
clocks.
Inputs
RS — Reset
F
IGURE
1.
O
FFSET
R
EGISTERS
LE
PAE LSB
PAE MSB
PAF LSB
PAF MSB
PAE LSB
PAE MSB
PAF LSB
PAF MSB
PAE LSB
PAE MSB
PAF LSB
PAF MSB
PAE LSB
PAE MSB
PAF LSB
PAF MSB
E
0
/F
O
are the least significant bits.
X = Don't Care.
2
L8C211 OFFSET REGISTERS
7
6
5
4
3
8
X E
7
E
6
E
5
E
4
E
3
X X X X X X
X F
7
F
6
F
5
F
4
F
3
X X X X X X
L8C221 OFFSET REGISTERS
7
6
5
4
3
8
X E
7
E
6
E
5
E
4
E
3
X X X X X X
X F
7
F
6
F
5
F
4
F
3
X X X X X X
BS
O
A reset occurs when RS is set LOW. A
reset is required after power-up before
a write operation can take place.
During reset, the internal read and
write pointers are set to the first
physical location, the output register is
initialized to zero, the offset registers
are initialized to their default values
(0007H), the Empty Flag (EF) and
Programmable Almost-Empty Flag
(PAE) are set LOW, the Full Flag (FF)
and Programmable Almost-Full Flag
(PAF) are set HIGH, and the WEN
2
/
LD signal is configured.
L8C231 OFFSET REGISTERS
7
6
5
4
3
2
8
X E
7
E
6
E
5
E
4
E
3
E
2
X X X X X X E
10
X F
7
F
6
F
5
F
4
F
3
F
2
X X X X X X F
10
L8C241 OFFSET REGISTERS
7
6
5
4
3
2
8
X E
7
E
6
E
5
E
4
E
3
E
2
X X X X X E
11
E
10
X F
7
F
6
F
5
F
4
F
3
F
2
X X X X X F
11
F
10
O
TE
2
E
2
X
F
2
X
1
E
1
X
F
1
X
0
E
0
E
8
F
0
F
8
2
E
2
X
F
2
X
1
E
1
E
9
F
1
F
9
0
E
0
E
8
F
0
F
8
1
E
1
E
9
F
1
F
9
0
E
0
E
8
F
0
F
8
1
E
1
E
9
F
1
F
9
0
E
0
E
8
F
0
F
8
FIFO Products
03/04/99–LDS.8C211/21/31/41-C
L8C211/221/231/241
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Synchronous FIFO
OE — Output Enable
When OE is LOW, the output port
(Q
8-0
) is enabled for output. When
OE is HIGH, Q
8-0
is placed in a high-
impedance state. The flag outputs are
not affected by OE.
Outputs
Q
8-0
— Data Output
Q
8-0
is the 9-bit registered data output
port.
FF — Full Flag
OPERATING MODES
Single Device Mode
A single FIFO may be used when the
application requirements are for the
number of words in a single device.
Width Expansion Mode
Word width may be increased simply
by connecting the corresponding input
control signals of multiple devices.
Any word width can be attained by
adding the appropriate number of
FIFOs. Status flags can be monitored
from any one of the devices.
Depth Expansion Mode
O
3
When WEN
2
/LD is configured to be
an offset register load/read control, it
is possible to write to or read from the
offset registers. The values stored in
the offset registers determine how the
Programmable Almost-Empty (PAE)
and Programmable Almost-Full (PAF)
Flags operate (see PAE and PAF
sections). There are four 9-bit offset
registers. Two are used to control the
Programmable Almost-Empty Flag
and two are used to control the
Programmable Almost-Full Flag (see
Figure 1). Data on D
8-0
is written to
an offset register on the rising edge of
WCLK if LD and WEN
1
are LOW.
After reset, data is written to the offset
registers in the following order: PAE
LSB, PAE MSB, PAF LSB, PAF MSB.
After the PAF MSB register has been
loaded, the sequence repeats starting
with the PAE LSB register. If register
loading is stopped, the next register in
sequence will be loaded when the next
register write occurs. If LD, REN
1
,
and REN
2
are LOW, data is read from
an offset register and presented on Q
8-0
(if the output port is enabled) after
t
D
has elapsed from the rising edge of
RCLK. The offset registers are read in
the same order they are written to. It
is not possible to read from and write
to the offset registers at the same time.
REN
1
, REN
2
— Read Enables 1 and 2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
The Full Flag goes LOW when the
FIFO is full of data. When FF is LOW,
the FIFO can not be written to. The
Full Flag is synchronized to the rising
edge of WCLK.
EF — Empty Flag
The Empty Flag goes LOW when the
read pointer is equal to the write
pointer, indicating that the FIFO is
empty. When EF is LOW, read opera-
tions can not be performed. The
Empty Flag is synchronized to the
rising edge of RCLK.
PAF — Programmable Almost-Full Flag
O
D
8-0
— Data Input
Data is read from the FIFO and pre-
sented on Q
8-0
after
t
D
has elapsed from
the rising edge of RCLK if REN
1
and
REN
2
are LOW and if the output port is
enabled. If either Read Enable goes
HIGH, the last value loaded in the
output register will remain unchanged.
The Read Enable signals are ignored
when the FIFO is empty.
D
8-0
is the 9-bit registered data input
port.
BS
PAF goes LOW when the write pointer
is (Full – N) locations ahead of the
read pointer. N is the value stored in
the PAF offset register and has a
default value of 7. PAF is synchro-
nized to the rising edge of WCLK.
PAE — Programmable Almost-Empty Flag
PAE goes HIGH when the write
pointer is (N + 1) locations ahead of
the read pointer. N is the value stored
in the PAE offset register and has a
default value of 7. PAE is synchro-
nized to the rising edge of RCLK.
LE
TE
The FIFOs can easily be adapted to
applications where the requirements
are for greater than the number of
words in a single device. If the FIFOs
are configured to use WEN
2
and
external logic is used to direct the flow
of data into the cascaded FIFOs, depth
expansion can be accomplished.
FIFO Products
03/04/99–LDS.8C211/21/31/41-C
L8C211/221/231/241
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Synchronous FIFO
M
AXIMUM
R
ATINGS
Above which useful life may be impaired (Notes 1, 2)
Storage temperature ........................................................................................................... –55°C to +125°C
Operating ambient temperature ................................................................................................. 0°C to +70°C
V
CC
supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V
Input signal with respect to ground ........................................................................................ –0.5 V to +7.0 V
Signal applied to high impedance output ............................................................................... –0.5 V to +7.0 V
Output current into low outputs ............................................................................................................. 50 mA
O
PERATING
C
ONDITIONS
To meet specified electrical and switching characteristics
E
LECTRICAL
C
HARACTERISTICS
Over Operating Conditions
V
OH
V
OL
V
IH
Output High Voltage
Output Low Voltage
Input High Voltage
V
CC
= 4.5 V,
I
OH
= –2.0 mA
V
CC
= 4.5 V,
I
OL
= 8.0 mA
LE
4
Symbol
Parameter
Test Condition
TE
Min
Typ
2.4
2.0
–1
–10
Mode
Active Operation, Commercial
Active Operation, Industrial
Temperature Range
(Ambient)
0°C to +70°C
–40°C to +85°C
Supply Voltage
4.5 V
≤
V
CC
≤
5.5 V
4.5 V
≤
V
CC
≤
5.5 V
L8C211/221/231/241
Max Unit
V
0.4
V
V
O
Ground
≤
V
IN
≤
V
CC
Ground
≤
V
OUT
≤
V
CC
Ambient Temp = 25°C,
V
CC
= 4.5 V
Test Frequency = 1 MHz
V
IL
I
IX
I
OZ
I
CC1
C
IN
C
OUT
Input Low Voltage
Input Leakage Current
Output Leakage Current
V
CC
Current, Active
Input Capacitance
0.8
+1
+10
90
10
10
V
µA
µA
mA
pF
pF
Output Capacitance
O
BS
FIFO Products
03/04/99–LDS.8C211/21/31/41-C
L8C211/221/231/241
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Synchronous FIFO
SWITCHING CHARACTERISTICS
Over Operating Range
R
ESET
T
IMING
Notes 3, 4, 5 (ns)
L8C211/221/231/241–
50
Symbol
t
RS
t
RSS
t
RSF
Parameter
Reset Pulse Width
Reset Setup Time
Reset to Flag and Output Valid
Min
50
50
50
Max
25
Min
25
25
25
Max
Min
20
20
20
20
Max
15
Min
15
15
15
Max
1
2
3
R
ESET
T
IMING
t
RS
RS
REN
1
REN
2
t
RSF
EF
PAE
FF
PAF
WEN
1
TE
t
RSS
4
5
6
7
8
9
10
11
12
13
14
WEN
2
/LD
t
RSF
Q
8-0
*
*after reset, Q
8-0
will be LOW if OE = 0 and in HIGH IMPEDANCE if OE = 1.
O
BS
FIFO Products
5
03/04/99–LDS.8C211/21/31/41-C
O
LE
t
RSS
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