®
X9118
Dual Supply/Low Power/1024-Tap/2-Wire Bus
Data Sheet
February 28, 2005
FN8161.0
PRELIMINARY
Single Digitally-Controlled (XDCP™)
Potentiometer
DESCRIPTION
The X9118 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.
The digital controlled potentiometer is implemented
using 1023 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
2-wire bus interface. The potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and a four non-volatile Data Registers that can
be directly written to and read by the user. The
contents of the WCR controls the position of the wiper
on the resistor array though the switches. Powerup
recalls the contents of the default data register (DR0)
to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
FUNCTIONAL DIAGRAM
FEATURES
• 1024 Resistor Taps – 10-Bit Resolution
• 2-Wire Serial Interface for write, read, and transfer
operations of the potentiometer
• Wiper Resistance, 40Ω Typical @ 5V
• Four Non-Volatile Data Registers for Each
Potentiometer
• Non-Volatile Storage of Multiple Wiper Positions
• Power On Recall. Loads Saved Wiper Position on Power
Up.
• Standby Current < 3µA Max
• System V
CC
: - 2.7V to 5.5V Operation
• Analog V+/V-: -5V to +5V
• 100kΩ End to End Resistance
• Endurance: 100, 000 Data changes per bit per register
• 100 yr. Data Retention
• 14-Lead TSSOP, 15-Lead CSP (Chip Scale Package).
Call factory for CSP availability
• Low power CMOS
V
CC
R
H
V+
2-Wire
Bus
Interface
Address
Data
Status
Bus
Interface &
Control
Write
Read
Transfer
Power On Recall
Wiper Counter
Register (WCR)
Data Registers
(DR0-DR3)
Wiper
100kΩ
1024-taps
POT
Control
V
SS
NC
NC
R
W
R
L
V-
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9118
DETAILED FUNCTIONAL DIAGRAM
V
CC
V+
Power On
Recall
SCL
SDA
A1
A0
DR0
Interface
and
Control
Circuitry
Data
DR2
Control
R
W
WP
DR3
DR1
Wiper
Counter
Register
(WCR)
100kΩ
1024-taps
R
L
R
H
V
SS
V-
CIRCUIT LEVEL APPLICATIONS
• Vary the gain of a voltage amplifier
• Provide programmable dc reference voltages for
comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier
circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and
Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback circuits
SYSTEM LEVEL APPLICATIONS
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in
communication systems
• Set and regulate the DC biasing point in an RF power
amplifier in wireless systems
• Control the gain in audio and home entertainment systems
• Provide the variable DC bias for tuners in RF wireless
systems
• Set the operating points in temperature control systems
• Control the operating point for sensors in industrial
systems
• Trim offset and gain errors in artificial intelligent systems
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FN8161.0
February 28, 2005
X9118
PIN CONFIGURATION
TSSOP
V+
NC
A0
SCL
WP
SDA
V
SS
14
1
13
2
3
12
X9118
4
11
5
10
6
9
8
7
V
CC
R
L
R
H
R
W
NC
A1
V-
Call Factory for
CSP Availability
X9118
CSP
PIN ASSIGNMENTS
PIN
(TSSOP)
PIN
(CSP)
SYMBOL
FUNCTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
V+
NC
A0
SCL
WP
SDA
V
SS
V
-
A1
NC
R
W
R
H
R
L
V
CC
Analog Supply Voltage
No Connect
Device Address for 2-wire bus
Serial Clock for 2-wire bus
Hardware Write Protect
Serial Data Input/Output for 2-wire bus
System Ground
Analog Supply Voltage
Device Address for 2-wire bus
No Connect
Wiper terminal of the Potentiometer
High terminal of the Potentiometer
Low terminal of the Potentiometer
System Supply Voltage
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FN8161.0
February 28, 2005
X9118
PIN DESCRIPTIONS
Bus Interface Pins
S
ERIAL
D
ATA
I
NPUT
/O
UTPUT
(SDA)
The SDA is a bidirectional serial data input/output pin
for a 2-wire slave device and is used to transfer data
into and out of the device. It receives device address,
opcode, wiper register address and data sent from an
2-wire master at the rising edge of the serial clock
SCL, and it shifts out data after each falling edge of
the serial clock SCL.
It is an open drain output and may be wire-ORed with
any number of open drain or open collector outputs.
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the
guidelines for calculating typical values on the bus
pull-up resistors graph.
S
ERIAL
C
LOCK
(SCL)
This input is used by 2-wire master to supply 2-wire
serial clock to the X9118.
D
EVICE
A
DDRESS
(A1–A0)
The address inputs are used to set the least significant
2 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
Address input in order to initiate communication with
the X9118. A maximum of 4 XDCP devices may
occupy the 2-wire serial bus.
H
ARDWARE
W
RITE
P
ROTECT
I
NPUT
(WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
Potentiometer Pins
R
H
, R
L
The R
H
and R
L
pins are equivalent to the terminal
connections on a mechanical potentiometer.
R
W
The wiper pin is equivalent to the wiper terminal of a
mechanical potentiometer.
Bias Supply Pins
S
YSTEM
S
UPPLY
V
OLTAGE
(V
CC
)
AND
S
UPPLY
G
ROUND
(V
SS
)
The V
CC
pin is the system or digital supply voltage.
The V
SS
pin is the system ground.
A
NALOG
S
UPPLY
V
OLTAGES
(V+
AND
V
-
)
These supplies are the analog voltage supplies for the
potentiometer. The V+ supply is tied to the wiper
switches while the V- supply is used to bias the
switches and the internal P+ substrate of the
integrated circuit. Both of these supplies set the
voltage limits of the potentiometer.
Other Pins
N
O
C
ONNECT
No connect pins should be left open. These pins are
used for Intersil manufacturing and testing purposes.
PRINCIPLES OF OPERATION
The X9118 is an integrated microcircuit incorporating
a resistor array and their its registers and counters and
the serial interface logic providing direct
communication between the host and the digitally
controlled potentiometer. This section provides detail
description of the following:
– Resistor Array Description
– Serial Interface Description
– Instruction and Register Description
Resistor Array Description
The X9118 is comprised of a resistor array. The array
contains 1023, in effect, discrete resistive segments
that are connected in series (see Figure 1). The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (R
H
and R
L
inputs).
At both ends of each array and between each resistor
segment is a CMOS switch (transmission gate)
connected to the wiper (R
W
) output. Within each
individual array only one switch may be turned on at a
time. These switches are controlled by the Wiper
Counter Register (WCR). The 10-bits of the WCR
(WCR[9:0]) are decoded to select, and enable, one of
1024 switches.
The WCR may be written directly. The Data Registers
and the WCR can be read and written by the host
system.
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FN8161.0
February 28, 2005
X9118
Figure 1. Detailed Potentiometer Block Diagram
Serial Data Path
From Interface
Circuitry
Register 0
(DR0)
10
Register 1
(DR1)
10
Serial
Bus
Input
C
O
U
N
T
E
R
D
E
C
O
D
E
RH
Parallel
Bus
Input
Wiper
Counter
Register
(WCR)
Register 2
(DR2)
Register 3
(DR3)
If WCR = 000[HEX] then R
W
= R
L
If WCR = 3FF[HEX] then R
W
= R
H
RL
R
W
Serial Interface Description
S
ERIAL
I
NTERFACE
– 2-W
IRE
The X9118 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9118 will be considered a
slave device in all applications.
C
LOCK AND
D
ATA
C
ONVENTIONS
Data states on the SDA line can change only during
SCL LOW periods. SDA state changes during SCL
HIGH are reserved for indicating start and stop
conditions. See Figure 3.
S
TART
C
ONDITION
All commands to the X9118 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH. The X9118 continuously monitors
the SDA and SCL lines for the start condition and will
not respond to any command until this condition is
met. See Figure 3.
S
TOP
C
ONDITION
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH. See Figure 3.
A
CKNOWLEDGE
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.
The X9118 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9118 will respond with a final acknowledge.
See Figure 2.
5
FN8161.0
February 28, 2005
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