Product Specification
PE3335
Product Description
Peregrine’s PE3335 is a high performance integer-N PLL
capable of frequency synthesis up to 3000 MHz. The
superior phase noise performance of the PE3335 makes it
ideal for applications such as LMDS / MMDS / WLL
basestations and demanding terrestrial systems.
The PE3335 features a 10/11 dual modulus prescaler,
counters, phase comparator and a charge pump as shown
in Figure 1. Counter values are programmable through
either a serial or parallel interface and can also be directly
hard wired.
The PE3335 Phase Locked-Loop is optimized for terrestrial
applications. It is manufactured on Peregrine’s
UltraCMOS™ process, a patented variation of silicon-on-
insulator (SOI) technology on a sapphire substrate, offering
the performance of GaAs with the economy and integration
of conventional CMOS.
3000 MHz UltraCMOS™ Integer-N PLL
for Low Phase Noise Applications
Features
•
3000 MHz operation
•
÷10/11 dual modulus prescaler
•
Internal phase detector with
charge pump
•
Serial, parallel or hardwired
programmable
•
Ultra-low phase noise
•
Available in 44-lead PLCC and
7x7 mm 48-lead QFN packages
Figure 1. Block Diagram
F
in
F
in
Prescaler
10/11
Main
Counter
13
f
p
D(7:0)
8
Sdata
Pre_en
M(6:0)
A(3:0)
R(3:0)
f
r
Primary
20-bit
20
Latch
Secon-
dary
20-bit
Latch
20
20
20
16
Phase
Detector
PD_U
PD_D
Charge
Pump
CP
6
6
f
c
R Counter
Document No. 70-0049-02
│
www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 15
PE3335
Product Specification
Figure 2. Pin Configurations (Top View)
GND
GND
GND
GND
GND
GND
Enh
V
DD
LD
R
3
R
2
R
1
R
0
fr
48 47 46 45 44 43 42 41 40 39 38 37
6
D
0
, M
0
D
1
, M
1
D
2
, M
2
D
3
, M
3
V
DD
V
DD
S_W R, D
4
, M
4
Sdata, D
5
, M
5
Sclk, D
6
, M
6
FSELS, D
7
, Pre_en
GND
5
4
3
2
1
44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
f
c
V
DD
_f
c
NC
CP
V
DD
C
ext
V
DD
D
out
V
DD
_f
p
f
p
GND
D0, M0
D1, M1
D2, M2
D3, M3
V
DD
V
DD
S_W R, D4, M4
Sdata, D5, M5
Sclk, D6, M6
FSELS, D7, Pre_en
GND
FSELP, A0
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
FSELP, A
0
E_WR, A
1
M2_WR, A
2
Smode, A
3
Bmode
V
DD
M1_WR
A_WR
Hop_WR
F
in
F
in
1
2
3
4
5
6
7
8
9
10
11
12
GND
Enh
V
DD
LD
R3
R2
R1
R0
f
r
36
35
34
33
32
31
30
29
28
27
26
25
f
c
V
DD
_f
c
NC
NC
CP
GND
V
DD
C
ext
V
DD
D
out
V
DD
_f
p
f
p
13 14 15 16 17 18 19 20 21 22 23 24
E_WR, A1
M2_WR, A2
Smode, A3
Bmode
V
DD
V
DD
M1_WR
A_WR
Hop_WR
Fin
Fin
GND
44-lead PLCC
Table 1. Pin Descriptions
Pin No.
(44-lead
PLCC)
1
2
3
4
5
6
7
48-lead QFN
Pin No.
(48-lead
QFN)
43
44
45
46
47
48
1
Pin
Name
V
DD
R
0
R
1
R
2
R
3
GND
D
0
M
0
D
1
Interface
Mode
ALL
Direct
Direct
Direct
Direct
ALL
Parallel
Direct
Parallel
Direct
Parallel
Direct
Parallel
Direct
ALL
ALL
Type
Description
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing
recommended.
R Counter bit0 (LSB).
R Counter bit1.
R Counter bit2.
R Counter bit3.
Ground.
Parallel data bus bit0 (LSB).
M Counter bit0 (LSB).
Parallel data bus bit1.
M Counter bit1.
Parallel data bus bit2.
M Counter bit2.
Parallel data bus bit3.
M Counter bit3.
Same as pin 1 (QFN48 pin 43).
Same as pin 1 (QFN48 pin 43).
Document No. 70-0049-02
│
UltraCMOS™ RFIC Solutions
(Note 1)
Input
Input
Input
Input
(Note 1)
Input
Input
Input
Input
Input
Input
Input
Input
(Note 1)
(Note 1)
8
2
M
1
D
2
9
3
M
2
D
3
10
11
12
4
M
3
5
6
V
DD
V
DD
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 15
PE3335
Product Specification
Table 1. Pin Descriptions (continued)
Pin No.
(44-lead
PLCC)
Pin No.
(48-lead
QFN)
Pin
Name
Interface
Mode
Type
Description
Serial load enable input. While S_WR is “low”, Sdata can be serially clocked.
Primary register data are transferred to the secondary register on S_WR or
Hop_WR rising edge.
Parallel data bus bit4
M Counter bit4
Binary serial data input. Input data entered MSB first.
Parallel data bus bit5.
M Counter bit5.
Serial clock input. Sdata is clocked serially into the 20-bit primary register
(E_WR “low”) or the 8-bit enhancement register (E_WR “high”) on the rising
edge of Sclk.
Parallel data bus bit6.
M Counter bit6.
Selects contents of primary register (FSELS=1) or secondary register
(FSELS=0) for programming of internal counters while in Serial Interface
Mode.
Parallel data bus bit7 (MSB).
Prescaler enable, active “low”. When “high”, F
in
bypasses the prescaler.
Ground.
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
(Note 1)
Input
Input
Input
Input
Selects contents of primary register (FSELP=1) or secondary register
(FSELP=0) for programming of internal counters while in Parallel Interface
Mode.
A Counter bit0 (LSB).
Enhancement register write enable. While E_WR is “high”, Sdata can be
serially clocked into the enhancement register on the rising edge of Sclk.
Enhancement register write. D[7:0] are latched into the enhancement register
on the rising edge of E_WR.
A Counter bit1.
M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the
rising edge of M2_WR.
A Counter bit2.
Selects serial bus interface mode (Bmode=0,
Smode=1) or Parallel Interface
Mode (Bmode=0, Smode=0).
A Counter bit3 (MSB).
Selects direct interface mode (Bmode=1).
Same as pin 1 (MLP48 pin 43).
M1 write. D[7:0] are latched into the primary register (Pre_en,
M[6:0]) on the
rising edge of M1_WR.
A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the
rising edge of A_WR.
Hop write. The contents of the primary register are latched into the
secondary register on the rising edge of Hop_WR.
Prescaler input from the VCO. 3.0 GHz max frequency.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 15
S_WR
13
7
D
4
M
4
Sdata
14
8
D
5
M
5
Sclk
15
9
D
6
M
6
FSELS
16
10
D
7
Pre_en
17
11
GND
FSELP
18
12
A
0
Serial
Parallel
Direct
Serial
Parallel
Direct
Serial
Parallel
Direct
Serial
Parallel
Direct
ALL
Parallel
Direct
Serial
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
E_WR
19
13
A
1
M2_WR
20
14
A
2
Smode
21
15
A
3
22
23
24
25
26
27
16
17,18
19
20
21
22
Bmode
V
DD
M1_WR
A_WR
Hop_WR
F
in
Direct
Serial,
Parallel
Direct
ALL
ALL
Parallel
Parallel
Serial,
Parallel
ALL
Parallel
Direct
Parallel
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PE3335
Product Specification
Table 1. Pin Descriptions (continued)
Pin No.
(44-lead
PLCC)
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Note 1:
Pin No.
(48-lead
QFN)
23
24
25
26
27
28
29
30
32
33, 34
35
36
31,37
38,39
40
41
42
Pin
Name
Interface
Mode
Type
Description
Prescaler complementary input. A bypass capacitor should be placed as
close as possible to this pin and be connected in series with a 50
Ω
resistor
directly to the ground plane.
Ground.
F
in
GND
f
p
V
DD
-f
p
Dout
V
DD
Cext
V
DD
CP
NC
V
DD
-f
c
f
c
GND
GND
f
r
LD
Enh
ALL
ALL
ALL
ALL
Serial,
Parallel
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
Serial,
Parallel
Input
Output
(Note 1)
Output
(Note 1)
Output
(Note 1)
Output
Monitor pin for main divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding V
DD
pin 31.
V
DD
for f
p
. Can be left floating or connected to GND to disable the f
p
output.
Data Out. The MSEL signal and the raw prescaler output are available on
Dout through enhancement register programming.
Same as pin 1 (QFN48 pin 43).
Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kΩ
series resistor. Connecting Cext to an external capacitor will low pass filter
the input to the inverting amplifier used for driving LD.
Same as pin 1 (QFN48 pin 43).
Charge pump current is sourced when f
c
leads f
p
and sinked when f
c
lags f
p
.
No connection.
(Note 1)
Output
V
DD
for f
c
can be left floating or connected to GND to disable the f
c
output.
Monitor pin for reference divider output. Switching activity can be disabled
through enhancement register programming or by floating or grounding V
DD
pin 38.
Ground.
Ground.
Input
Output
Input
Reference frequency input.
Lock detect and open drain logical inversion of Cext. When the loop is in lock,
LD is high impedance, otherwise LD is a logic low (“0”).
Enhancement mode. When asserted low (“0”), enhancement register bits are
functional.
All V
DD
pins are connected by diodes and must be supplied with the same positive voltage level.
V
DD
-f
p
and V
DD
-f
c
are used to power the f
p
and f
c
outputs and can alternatively be left floating or connected to GND to disable the f
p
and f
c
outputs.
Note 2:
All digital input pins have 70 kΩ pull-down resistors to ground.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 15
Document No. 70-0049-02
│
UltraCMOS™ RFIC Solutions
PE3335
Product Specification
Table 2. Absolute Maximum Ratings
Symbol
V
DD
V
I
I
I
I
O
T
stg
Table 4. ESD Ratings
Units
V
V
Note 1:
mA
mA
°C
Periodically sampled, not 100% tested. Tested per MIL-
STD-883, M3015 C2
Parameter/Conditions
Supply voltage
Voltage on any input
DC into any input
DC into any output
Storage temperature range
Min
-0.3
-0.3
-10
-10
-65
Max
4.0
V
DD
+
0.3
+10
+10
150
Symbol
V
ESD
Parameter/Conditions
ESD voltage (Human Body
Level
1000
Units
V
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating in Table 4.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Table 3. Operating Ratings
Symbol
V
DD
T
A
Parameter/Conditions
Supply voltage
Operating ambient
temperature range
Min
2.85
-40
Max
3.15
85
Units
V
°C
Table 5. DC Characteristics:
V
DD
= 3.0 V, -40° C < T
A
< 85° C, unless otherwise specified
Symbol
I
DD
Parameter
Operational supply current;
Prescaler disabled
Prescaler enabled
Conditions
V
DD
= 2.85 to 3.15 V
Min
Typ
10
24
Max
Units
mA
mA
V
V
µA
µA
µA
µA
µA
µA
V
V
V
V
V
mA
mA
µA
%
%
31
Digital Inputs: All except f
r
, R
0
, F
in
,
F
in
V
IH
High level input voltage
V
IL
Low level input voltage
I
IH
I
IL
High level input current
Low level input current
V
DD
= 2.85 to 3.15 V
V
DD
= 2.85 to 3.15 V
V
IH
= V
DD
= 3.15 V
V
IL
= 0, V
DD
= 3.15 V
V
IH
= V
DD
= 3.15 V
V
IL
= 0, V
DD
= 3.15 V
V
IH
= V
DD
= 3.15 V
V
IL
= 0, V
DD
= 3.15 V
I
out
= 6 mA
I
out
= -3 mA
I
out
= 100 mA
I
out
= -100 mA
I
out
= 6 mA
V
CP
= V
DD
/ 2
V
CP
= V
DD
/ 2
1.0 V < V
CP
< V
DD
– 1.0 V
VCP = V
DD
/ 2,
T
A
= 25° C
V < V
CP
< V
DD
– 1.0 V
T
A
= 25° C
0.7 x V
DD
0.3 x V
DD
+70
-1
+100
-100
+5
-5
0.4
V
DD
- 0.4
0.4
V
DD
- 0.4
0.4
-2.6
1.4
-1
-2
2
1
-1.4
2.6
15
15
Reference Divider input: f
r
I
IHR
High level input current
I
ILR
Low level input current
R0 Input (Pull-up Resistor): R
0
I
IHRO
High level input current
I
ILRO
Low level input current
Counter output D
out
V
OLD
Output voltage LOW
V
OHD
Output voltage HIGH
Lock detect outputs: Cext, LD
V
OLC
Output voltage LOW, Cext
V
OHC
Output voltage HIGH, Cext
V
OLLD
Output voltage LOW, LD
Charge Pump output: CP
I
CP
- Source
I
CP
– Sink
I
CPL
I
CP
– Source
vs. I
CP
Sink
I
CP
vs. V
CP
Drive current
Drive current
Leakage current
Sink vs. source mismatch
Output current magnitude variation vs. voltage
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©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 15
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